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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-07-11 07:55:21 +0300
committerPatrick Georgi <patrick@georgi-clan.de>2012-07-16 18:41:46 +0200
commitcc55b9b9199657834a946ea2de059c3fab3e3b10 (patch)
tree732d9757212623855ba25e0d925d292d441b5098 /src/southbridge/amd/rs690
parent63f8c088307c5296809d9499b3b7cbaedb2a4440 (diff)
downloadcoreboot-cc55b9b9199657834a946ea2de059c3fab3e3b10.tar.xz
Define global uma_memory variables
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/rs690')
-rw-r--r--src/southbridge/amd/rs690/cmn.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c
index 5e06d4f9d8..68c46e9728 100644
--- a/src/southbridge/amd/rs690/cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
@@ -315,8 +315,6 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
*/
void rs690_set_tom(device_t nb_dev)
{
- extern uint64_t uma_memory_base;
-
/* set TOM */
pci_write_config32(nb_dev, 0x90, uma_memory_base);
nbmc_write_index(nb_dev, 0x1e, uma_memory_base);