Add AMD rs690 VID DID reporting and some minor cleanups.

Signed-off-by:  Joe Bao <zheng.bao@amd.com>
Reviewed-by:    Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 50 insertions, 116 deletions

diff --git a/src/southbridge/amd/rs690/chip.h b/src/southbridge/amd/rs690/chip.h
index 9eb71aa0b3..176b744fe0 100644
--- a/src/southbridge/amd/rs690/chip.h
+++ b/src/southbridge/amd/rs690/chip.h
@@ -21,9 +21,9 @@
 #define RS690_CHIP_H
 
 /* Member variables are defined in Config.lb. */
-struct southbridge_amd_rs690_config 
+struct southbridge_amd_rs690_config
 {
-	unsigned long vga_rom_address;		/* The location that the VGA rom has been appened. */
+	u32 vga_rom_address;		/* The location that the VGA rom has been appened. */
 	u8 gpp_configuration;	/* The configuration of General Purpose Port, A/B/C/D/E. */
 	u8 port_enable;		/* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
 	u8 gfx_dev2_dev3;	/* for GFX Core initialization REFCLK_SEL */
diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c
index dab5167d94..3caa00e9c8 100644
--- a/src/southbridge/amd/rs690/rs690.c
+++ b/src/southbridge/amd/rs690/rs690.c
@@ -29,25 +29,6 @@
 #include <cpu/amd/mtrr.h>
 #include "rs690.h"
 
-static device_t find_nb_dev(device_t dev, u32 devfn)
-{
-	device_t nb_dev;
-
-	nb_dev = dev_find_slot(dev->bus->secondary, devfn);
-
-	if (!nb_dev)
-		return nb_dev;
-
-	if ((nb_dev->vendor != PCI_VENDOR_ID_ATI)
-	    || (nb_dev->device != PCI_DEVICE_ID_ATI_RS690_HT)) {
-		u32 id;
-		id = pci_read_config32(nb_dev, PCI_VENDOR_ID);
-		if (id != (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_RS690_HT << 16))) {
-			nb_dev = 0;
-		}
-	}
-	return nb_dev;
-}
 
 /*****************************************
 * Compliant with CIM_33's ATINB_MiscClockCtrl
@@ -65,7 +46,7 @@ void static rs690_config_misc_clk(device_t nb_dev)
 
 	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
 	word &= 0xf00;
-	 pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
+	pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
 
 	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
 	word &= ~((1 << 12) | (1 << 13) | (1 << 14));
@@ -123,6 +104,12 @@ void static rs690_config_misc_clk(device_t nb_dev)
 	set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
 }
 
+
+u32 get_vid_did(device_t dev)
+{
+	return pci_read_config32(dev, 0);
+}
+
 /***********************************************
 *	0:00.0  NBCFG	:
 *	0:00.1  CLK	: bit 0 of nb_cfg 0x4c : 0 - disable, default
@@ -140,39 +127,25 @@ void static rs690_config_misc_clk(device_t nb_dev)
 void rs690_enable(device_t dev)
 {
 	device_t nb_dev = 0, sb_dev = 0;
-	int index = -1;
-	u32 i;
-	u32 devfn;
-	u32 deviceid, vendorid;
-
-	vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
-	deviceid = (vendorid >> 16) & 0xffff;
-	vendorid &= 0xffff;
-	printk_info("rs690_enable VID=0x%x, DID=0x%x\n", vendorid, deviceid);
-
-	/**********************************************************
-	* Work for bus0, internal GFX located on bus1 and will return after find_nb_dev.
-	**********************************************************/
-	i = (dev->path.u.pci.devfn) & ~7;
-	for (devfn = 0; devfn <= i; devfn += (1 << 3)) {
-		nb_dev = find_nb_dev(dev, devfn);
-		if (nb_dev)
-			break;
-	}
+	int dev_ind;
+
+	printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev));
+
+	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!nb_dev) {
-		printk_info("CAN NOT FIND RS690 DEVICE!\n");
-		return;		/* nb_dev is not dev */
+		die("rs690_enable: CAN NOT FIND RS690 DEVICE, HALT!\n");
+		/* NOT REACHED */
 	}
 
 	/* sb_dev (dev 8) is a bridge that links to southbridge. */
 	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
 	if (!sb_dev) {
-		printk_info("rs690_enable CAN NOT FIND SB bridge, HALT!\n");
-		for (;;) ;
+		die("rs690_enable: CAN NOT FIND SB bridge, HALT!\n");
+		/* NOT REACHED */
 	}
 
-	printk_info("rs690_enable bus0, dev=0x%x\n", (dev->path.u.pci.devfn - devfn) >> 3);
-	switch (dev->path.u.pci.devfn - devfn) {
+	dev_ind = dev->path.u.pci.devfn >> 3;
+	switch (dev_ind) {
 	case 0:		/* bus0, dev0, fun0; */
 		printk_info("Bus-0, Dev-0, Fun-0.\n");
 		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
@@ -185,36 +158,34 @@ void rs690_enable(device_t dev)
 		rs690_config_misc_clk(nb_dev);
 		break;
 
-	case 1 << 3:		/* bus0, dev1 */
+	case 1:		/* bus0, dev1 */
 		printk_info("Bus-0, Dev-1, Fun-0.\n");
 		break;
-	case 2 << 3:		/* bus0, dev2,3, two GFX */
-	case 3 << 3:
+	case 2:		/* bus0, dev2,3, two GFX */
+	case 3:
 		printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
-		index = (dev->path.u.pci.devfn - devfn) >> 3;
-		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
-				       (dev->enabled ? 0 : 1) << index);
+		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
+				       (dev->enabled ? 0 : 1) << dev_ind);
 		if (dev->enabled)
-			rs690_gfx_init(nb_dev, dev, index);
+			rs690_gfx_init(nb_dev, dev, dev_ind);
 		break;
-	case 4 << 3:		/* bus0, dev4-7, four GPP */
-	case 5 << 3:
-	case 6 << 3:
-	case 7 << 3:
+	case 4:		/* bus0, dev4-7, four GPP */
+	case 5:
+	case 6:
+	case 7:
 		printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
 			    dev->enabled);
-		index = (dev->path.u.pci.devfn - devfn) >> 3;
-		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
-				       (dev->enabled ? 0 : 1) << index);
+		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
+				       (dev->enabled ? 0 : 1) << dev_ind);
 		if (dev->enabled)
-			rs690_gpp_sb_init(nb_dev, dev, index);
+			rs690_gpp_sb_init(nb_dev, dev, dev_ind);
 		break;
-	case 8 << 3:		/* bus0, dev8, SB */
+	case 8:		/* bus0, dev8, SB */
 		printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
 				       (dev->enabled ? 1 : 0) << 6);
 		if (dev->enabled)
-			rs690_gpp_sb_init(nb_dev, dev, index);
+			rs690_gpp_sb_init(nb_dev, dev, dev_ind);
 		disable_pcie_bar3(nb_dev);
 		break;
 	default:
diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c
index 0ed377695e..b714dc87c5 100644
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/rs690_cmn.c
@@ -63,8 +63,8 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
 
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c);
-	printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
-		     dev->path.u.pci.devfn);
+	/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.u.pci.devfn);*/
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.u.pci.devfn << 12 | reg_pos;
 
diff --git a/src/southbridge/amd/rs690/rs690_early_setup.c b/src/southbridge/amd/rs690/rs690_early_setup.c
index 7e11fde5eb..08ce2515c4 100644
--- a/src/southbridge/amd/rs690/rs690_early_setup.c
+++ b/src/southbridge/amd/rs690/rs690_early_setup.c
@@ -18,7 +18,6 @@
  */
 
 
- 
 #define NBHTIU_INDEX		0xA8
 #define NBMISC_INDEX		0x60
 #define NBMC_INDEX 		0xE8
@@ -185,7 +184,7 @@ static void rs690_htinit()
 	* get k8's ht freq, in k8's function 0, offset 0x88
 	* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
 	* The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
-	* value to this reg, and that value takes effect on the next warm reset or 
+	* value to this reg, and that value takes effect on the next warm reset or
 	* LDTSTOP_L disconnect sequence.
 	* 0000b = 200Mhz
 	* 0010b = 400Mhz
@@ -300,7 +299,7 @@ static void rs690_por_pcicfg_init(device_t nb_dev)
 	/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
 	 * force this BAR as mem type in rs690_gfx.c */
 	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
-	
+
 }
 
 /*****************************************
diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c
index 9b5929611b..ebddda2b51 100644
--- a/src/southbridge/amd/rs690/rs690_gfx.c
+++ b/src/southbridge/amd/rs690/rs690_gfx.c
@@ -72,7 +72,7 @@ static void rs690_gfx_read_resources(device_t dev)
 
 static void internal_gfx_pci_dev_init(struct device *dev)
 {
-	unsigned short deviceid, vendorid;
+	u16 deviceid, vendorid;
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)dev->chip_info;
 	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
@@ -109,11 +109,6 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	clkind_write(dev, 0x5C, 0x0);
 }
 
-static void rs690_gfx_set_resources(struct device *dev)
-{
-	printk_info("rs690_gfx_set_resources.\n");
-	pci_dev_set_resources(dev);
-}
 
 /*
 * Set registers in RS690 and CPU to enable the internal GFX.
@@ -137,7 +132,7 @@ static void rs690_internal_gfx_enable(device_t dev)
 
 	/* set TOM */
 	rs690_set_tom(nb_dev);
-	
+
 	/* LPC DMA Deadlock workaround? */
 	k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 	l_dword = pci_read_config32(k8_f0, 0x68);
@@ -206,9 +201,9 @@ static struct pci_operations lops_pci = {
 	.set_subsystem = pci_dev_set_subsystem,
 };
 
-static struct device_operations ht_ops = {
+static struct device_operations pcie_ops = {
 	.read_resources = rs690_gfx_read_resources,
-	.set_resources = rs690_gfx_set_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = internal_gfx_pci_dev_init,	/* The option ROM initializes the device. rs690_gfx_init, */
 	.scan_bus = 0,
@@ -216,8 +211,8 @@ static struct device_operations ht_ops = {
 	.ops_pci = &lops_pci,
 };
 
-static struct pci_driver internal_gfx_driver __pci_driver = {
-	.ops = &ht_ops,
+static struct pci_driver pcie_driver __pci_driver = {
+	.ops = &pcie_ops,
 	.vendor = PCI_VENDOR_ID_ATI,
 	.device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX,
 };
@@ -350,7 +345,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
 }
 
 
-/* For single port GFX configuration Only 
+/* For single port GFX configuration Only
 * width:
 * 	000 = x16
 * 	001 = x1
@@ -492,7 +487,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
 	printk_info("rs690_gfx_init step8.3.\n");
 
-	/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still 
+	/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still
 	 * time out and go back to Detect Idle.*/
 	set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14);
 	printk_info("rs690_gfx_init step8.4.\n");
@@ -510,7 +505,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30);
 	printk_info("rs690_gfx_init step8.8.\n");
 
-	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM. 
+	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
 	 * SLOT_IMPLEMENTED@PCIE_CAP */
 	reg16 = pci_read_config16(dev, 0x5a);
 	reg16 |= 0x100;
@@ -563,7 +558,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 
 	/* step 10.e: LCLK clock gating, done in rs690_config_misc_clk() */
 
-	/* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration.  
+	/* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration.
 	 * While details will be added later in the document, for now assue the single-port configuration. */
 	/* skip */
 
diff --git a/src/southbridge/amd/rs690/rs690_ht.c b/src/southbridge/amd/rs690/rs690_ht.c
index 808a7225a5..40a85f6c17 100644
--- a/src/southbridge/amd/rs690/rs690_ht.c
+++ b/src/southbridge/amd/rs690/rs690_ht.c
@@ -61,7 +61,7 @@ static void pcie_init(struct device *dev)
 	dword |= (1 << 30);	/* Clear possible errors */
 	pci_write_config32(dev, 0x04, dword);
 
-	/* 
+	/*
 	 * 1 is APIC enable
 	 * 18 is enable nb to accept A4 interrupt request from SB.
 	 */
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c
index 7b09a935d9..5e80849d7f 100644
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/rs690_pcie.c
@@ -116,37 +116,6 @@ static void pcie_init(struct device *dev)
 	pci_write_config32(dev, 0x04, dword);
 }
 
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations pcie_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init = pcie_init,
-	.scan_bus = pci_scan_bridge,
-	/*.enable           = rs690_enable, */
-	.ops_pci = &lops_pci,
-};
-
-static struct pci_driver pcie_driver __pci_driver = {
-	.ops = &pcie_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_RS690_PCIE,
-};
-
-static struct pci_driver pcie_driver_dev7 __pci_driver = {
-	.ops = &pcie_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7,
-};
-static struct pci_driver pcie_driver_dev8 __pci_driver = {
-	.ops = &pcie_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8,
-};
-
 /**********************************************************************
 **********************************************************************/
 static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)