diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-28 21:20:04 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:29:13 +0200 |
| commit | 1bcd7fcb6199528fc82685e161d6b39f273a1962 (patch) | |
| tree | 90e07ca28aa8514375b27b9c638a33701f921d52 /src/southbridge/amd/rs690 | |
| parent | 15279a9696c70b82c2223264a505da9122f9aa7b (diff) | |
| download | coreboot-1bcd7fcb6199528fc82685e161d6b39f273a1962.tar.xz | |
src/southbridge: Capitalize CPU, RAM and ROM
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15941
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Diffstat (limited to 'src/southbridge/amd/rs690')
| -rw-r--r-- | src/southbridge/amd/rs690/early_setup.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs690/rs690.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs690/early_setup.c b/src/southbridge/amd/rs690/early_setup.c index 7e17807f94..ec14073cff 100644 --- a/src/southbridge/amd/rs690/early_setup.c +++ b/src/southbridge/amd/rs690/early_setup.c @@ -279,7 +279,7 @@ static void rs690_por_pcicfg_init(device_t nb_dev) /* Power Management Register Enable */ set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80); - /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge + /* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation * BMMsgEn */ set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1); diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c index 453dd80ee6..f0c8134bac 100644 --- a/src/southbridge/amd/rs690/rs690.c +++ b/src/southbridge/amd/rs690/rs690.c @@ -116,7 +116,7 @@ static u32 get_vid_did(device_t dev) * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 -* case 0 will be called twice, one is by cpu in hypertransport.c line458, +* case 0 will be called twice, one is by CPU in hypertransport.c line458, * the other is by rs690. ***********************************************/ void rs690_enable(device_t dev) |