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authorZheng Bao <zheng.bao@amd.com>2010-03-16 01:41:14 +0000
committerZheng Bao <Zheng.Bao@amd.com>2010-03-16 01:41:14 +0000
commit1088bbff4503df7e8507aae45da823268262ca8f (patch)
tree414123cac2bdd5f70b10d64082b792e7a52e2c45 /src/southbridge/amd/rs780/Makefile.inc
parenteff2ffdee8489f97b265b0335b766be3db9a633a (diff)
downloadcoreboot-1088bbff4503df7e8507aae45da823268262ca8f.tar.xz
Features supported in RS780 code:
* PCIe initialization. * Internal Graphics initialization. * HT Link initialization. It works in HT1 or HT3 mode. Note: 1. I tried to add the description of every step to the code. For example, if it is made based on rpr, section 2.4.5, I will pasted the words from 2.4.5 to the c code. But the document I worked with might be different with the most updated one. A new section has been added and the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I correct every comment if I met one. But I have to confess that I am so reluctant to find out everyone. I believe it will be correct in the long run. 2. The interanl graphics part is done by Libo Feng <libo.feng@amd.com>. 3. There is a conflict between RPR and our CIM code. Please see the comment in switching_gppsb_configurations in rs780_pcie.c. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/rs780/Makefile.inc')
-rw-r--r--src/southbridge/amd/rs780/Makefile.inc5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc
new file mode 100644
index 0000000000..3d6fad10e3
--- /dev/null
+++ b/src/southbridge/amd/rs780/Makefile.inc
@@ -0,0 +1,5 @@
+driver-y += rs780.o
+driver-y += rs780_cmn.o
+driver-y += rs780_pcie.o
+driver-y += rs780_ht.o
+driver-y += rs780_gfx.o