sb/amd/rs780: Get rid of device_t

Change-Id: Ica3b6f2d0b270930df77d528e70bd15972da8757
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 42 insertions, 32 deletions

diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index 37c88e2058..971637b285 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -16,6 +16,7 @@
 #ifndef __RS780_H__
 #define __RS780_H__
 
+#include <rules.h>
 #include <stdint.h>
 #include <device/pci_ids.h>
 #include "chip.h"
@@ -170,47 +171,56 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
 * ------------------------------------------------- */
 extern PCIE_CFG AtiPcieCfg;
 
+#if ENV_RAMSTAGE
 /* ----------------- export functions ----------------- */
-u32 nbmisc_read_index(device_t nb_dev, u32 index);
-void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);
-u32 nbpcie_p_read_index(device_t dev, u32 index);
-void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
-u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
-void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
-u32 htiu_read_index(device_t nb_dev, u32 index);
-void htiu_write_index(device_t nb_dev, u32 index, u32 data);
-u32 nbmc_read_index(device_t nb_dev, u32 index);
-void nbmc_write_index(device_t nb_dev, u32 index, u32 data);
-
-u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
-void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
-
-void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
-void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val);
-void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
-void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
-void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
-void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val);
-void rs780_set_tom(device_t nb_dev);
+u32 nbmisc_read_index(struct device * nb_dev, u32 index);
+void nbmisc_write_index(struct device * nb_dev, u32 index, u32 data);
+u32 nbpcie_p_read_index(struct device * dev, u32 index);
+void nbpcie_p_write_index(struct device * dev, u32 index, u32 data);
+u32 nbpcie_ind_read_index(struct device * nb_dev, u32 index);
+void nbpcie_ind_write_index(struct device * nb_dev, u32 index, u32 data);
+u32 htiu_read_index(struct device * nb_dev, u32 index);
+void htiu_write_index(struct device * nb_dev, u32 index, u32 data);
+u32 nbmc_read_index(struct device * nb_dev, u32 index);
+void nbmc_write_index(struct device * nb_dev, u32 index, u32 data);
+
+u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg);
+void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg, u32 mask, u32 val);
+
+void set_nbcfg_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_nbcfg_enable_bits_8(struct device * nb_dev, u32 reg_pos, u8 mask, u8 val);
+void set_nbmc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_htiu_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
+
+void set_nbmisc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
+
+void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val);
+void rs780_set_tom(struct device *nb_dev);
 
 void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
-void enable_pcie_bar3(device_t nb_dev);
-void disable_pcie_bar3(device_t nb_dev);
-
-void rs780_enable(device_t dev);
-void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
-void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port);
-void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
-void config_gpp_core(device_t nb_dev, device_t sb_dev);
-void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
-u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
+void enable_pcie_bar3(struct device *nb_dev);
+void disable_pcie_bar3(struct device *nb_dev);
+
+void rs780_enable(struct device *dev);
+void rs780_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port);
+void rs780_gfx_init(struct device *nb_dev, struct device *dev, u32 port);
+void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev);
+void config_gpp_core(struct device *nb_dev, struct device *sb_dev);
+void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port);
+u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port);
+
+void pcie_hide_unused_ports(struct device *nb_dev);
+
+#endif
+
 u32 extractbit(u32 data, int bit_number);
 u32 extractbits(u32 source, int lsb, int msb);
 int cpuidFamily(void);
 int is_family0Fh(void);
 int is_family10h(void);
-void pcie_hide_unused_ports(device_t nb_dev);
+
 void enable_rs780_dev8(void);
 void rs780_early_setup(void);
 void rs780_htinit(void);
+
 #endif /* __RS780_H__ */