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| author | Zheng Bao <zheng.bao@amd.com> | 2010-03-23 06:46:01 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-03-23 06:46:01 +0000 |
| commit | b63bdbe29bd8bbc4756369792cc271ef6efa5e34 (patch) | |
| tree | 9ca6203ce30515cb54aab7b1b6d44f06ded2a4f3 /src/southbridge/amd/rs780/rs780_cmn.c | |
| parent | c8c09bb23942762ab9bc5e645b696bbad631628f (diff) | |
| download | coreboot-b63bdbe29bd8bbc4756369792cc271ef6efa5e34.tar.xz | |
Remove the building warnings.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/rs780/rs780_cmn.c')
| -rw-r--r-- | src/southbridge/amd/rs780/rs780_cmn.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/rs780_cmn.c index ab91074ad2..65dbcb9703 100644 --- a/src/southbridge/amd/rs780/rs780_cmn.c +++ b/src/southbridge/amd/rs780/rs780_cmn.c @@ -252,8 +252,8 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) u32 lc_state, reg, current_link_width, lane_mask; int8_t current, res = 0; u32 gfx_gpp_sb_sel; - void set_pcie_dereset(); - void set_pcie_reset(); + void set_pcie_dereset(void); + void set_pcie_reset(void); switch (port) { case 2 ... 3: @@ -265,6 +265,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) case 9 ... 10: gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP; break; + default: + gfx_gpp_sb_sel = -1; + return 0; } while (count--) { |