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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-12 10:54:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 12:51:26 +0000
commit400ce55566caa541304b2483e61bcc2df941998c (patch)
tree4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/southbridge/amd/rs780
parente64a585374de88ea896ed517445a34986aa321b9 (diff)
downloadcoreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/southbridge/amd/rs780')
-rw-r--r--src/southbridge/amd/rs780/early_setup.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index ab75e5f57f..865b577279 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -18,6 +18,7 @@
#include <northbridge/amd/amdmct/mct/mct_d.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
#include "rev.h"
#include "rs780.h"
@@ -317,10 +318,10 @@ static void k8_optimization(void)
set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
- msr = rdmsr(0xC001001F);
+ msr = rdmsr(NB_CFG_MSR);
msr.lo &= ~(1 << 9);
msr.hi &= ~(1 << 4);
- wrmsr(0xC001001F, msr);
+ wrmsr(NB_CFG_MSR, msr);
}
#else
#define k8_optimization() do {} while (0)