Remove the building warnings.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 58 insertions, 104 deletions

diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index 471603f865..3d23a453cd 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -107,12 +107,12 @@ void static rs780_config_misc_clk(device_t nb_dev)
 	set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
 }
 
-u32 get_vid_did(device_t dev)
+static u32 get_vid_did(device_t dev)
 {
 	return pci_read_config32(dev, 0);
 }
 
-void rs780_nb_pci_table(device_t nb_dev)
+static void rs780_nb_pci_table(device_t nb_dev)
 {	/* NBPOR_InitPOR function. */
 	u8 temp8;
 	u16 temp16;
@@ -191,7 +191,7 @@ void rs780_nb_pci_table(device_t nb_dev)
 #endif
 }
 
-void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
+static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 {
 	/* NB_InitGFXStraps */
 	u32 MMIOBase, apc04, apc18, apc24;
@@ -214,27 +214,27 @@ void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 	pci_write_config8(dev, 0x04, 0x02);
 
 	/* Program Straps. */
-	strap = MMIOBase + 0x15020;
+	strap = (volatile u32 *)(MMIOBase + 0x15020);
 #if (CONFIG_GFXUMA == 1)
 	*strap = 1<<7; /* the format of BIF_MEM_AP_SIZE. 001->256MB? */
 #else
 	*strap = 0; /* 128M SP memory, 000 -> 128MB */
 #endif
-	strap = MMIOBase + 0x15000;
+	strap = (volatile u32 *)(MMIOBase + 0x15000);
 	*strap = 0x2c006300;
-	strap = MMIOBase + 0x15010;
+	strap = (volatile u32 *)(MMIOBase + 0x15010);
 	*strap = 0x03015330;
-	//strap = MMIOBase + 0x15020;
+	//strap = (volatile u32 *)(MMIOBase + 0x15020);
 	//*strap |= 0x00000040; /* Disable HDA device. */
-	strap = MMIOBase + 0x15030;
+	strap = (volatile u32 *)(MMIOBase + 0x15030);
 	*strap = 0x00001002;
-	strap = MMIOBase + 0x15040;
+	strap = (volatile u32 *)(MMIOBase + 0x15040);
 	*strap = 0x00000000;
-	strap = MMIOBase + 0x15050;
+	strap = (volatile u32 *)(MMIOBase + 0x15050);
 	*strap = 0x00000000;
-	strap = MMIOBase + 0x15220;
+	strap = (volatile u32 *)(MMIOBase + 0x15220);
 	*strap = 0x03c03800;
-	strap = MMIOBase + 0x15060;
+	strap = (volatile u32 *)(MMIOBase + 0x15060);
 	*strap = 0x00000000;
 
 	/* BIF switches into normal functional mode. */
diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/rs780_cmn.c
index ab91074ad2..65dbcb9703 100644
--- a/src/southbridge/amd/rs780/rs780_cmn.c
+++ b/src/southbridge/amd/rs780/rs780_cmn.c
@@ -252,8 +252,8 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 	u32 lc_state, reg, current_link_width, lane_mask;
 	int8_t current, res = 0;
 	u32 gfx_gpp_sb_sel;
-	void set_pcie_dereset();
-	void set_pcie_reset();
+	void set_pcie_dereset(void);
+	void set_pcie_reset(void);
 
 	switch (port) {
 	case 2 ... 3:
@@ -265,6 +265,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 	case 9 ... 10:
 		gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP;
 		break;
+	default:
+		gfx_gpp_sb_sel = -1;
+		return 0;
 	}
 
 	while (count--) {
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c
index 808bcb175f..2ec0683ebe 100644
--- a/src/southbridge/amd/rs780/rs780_gfx.c
+++ b/src/southbridge/amd/rs780/rs780_gfx.c
@@ -35,8 +35,8 @@
 #include <cpu/x86/msr.h>
 #include "rs780.h"
 
-void set_pcie_reset();
-void set_pcie_dereset();
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
 
 #define CLK_CNTL_INDEX	0x8
 #define CLK_CNTL_DATA	0xC
@@ -89,7 +89,7 @@ typedef struct _MMIORANGE
 
 MMIORANGE MMIO[8], CreativeMMIO[8];
 
-MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
+static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
 {
 	int i;
 	for (i=0; i<8; i++)
@@ -99,7 +99,7 @@ MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
 	}
 	return 0;
 }
-void FreeMMIO(MMIORANGE* pMMIO)
+static void FreeMMIO(MMIORANGE* pMMIO)
 {
 	pMMIO->Base = 0;
 	pMMIO->Limit = 0;
@@ -115,7 +115,7 @@ void FreeMMIO(MMIORANGE* pMMIO)
 #define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
 #define MMIO_ATTRIB_SKIP_ZERO 1<<2
 
-u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
+static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 {
 	int i;
 	MMIORANGE * TempRange;
@@ -139,7 +139,7 @@ u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 	return 0;
 }
 
-u8 FinalizeMMIO(MMIORANGE *pMMIO)
+static u8 FinalizeMMIO(MMIORANGE *pMMIO)
 {
 	int i, j, n = 0;
 	for(i=0; i<8; i++)
@@ -173,7 +173,7 @@ u8 FinalizeMMIO(MMIORANGE *pMMIO)
 	return n;
 }
 
-CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
+static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
 {
 	CIM_STATUS Status = CIM_UNSUPPORTED;
 	u8 Bus, Dev, Reg, BusStart, BusEnd;
@@ -241,11 +241,10 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
 	return Status;
 }
 
-void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
+static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
 {
 	int i, j, n = 7;
 	device_t k8_f1;
-	u32 temp32;
 
 	k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 
@@ -296,17 +295,15 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	volatile u32 * pointer;
 	int i;
 	u16 command;
-	u32 value, temp, Base32, Limit32;
-	CIM_STATUS Status;
+	u32 value;
 	u16 deviceid, vendorid;
 	device_t nb_dev = dev_find_slot(0, 0);
 	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
-	device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
 
-	struct southbridge_amd_rs780_config *cfg =
-	    (struct southbridge_amd_rs780_config *)dev->chip_info;
+	/* We definetely will use this in future. Just leave it here. */
+	/*struct southbridge_amd_rs780_config *cfg =
+	   (struct southbridge_amd_rs780_config *)dev->chip_info;*/
 
 	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
 	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
@@ -430,7 +427,8 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	//vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1;
 	vgainfo.ulBootUpReqDisplayVector = 0; //?
 	vgainfo.ulOtherDisplayMisc = 0; //?
-	vgainfo.ulDDISlot1Config = 0x000c0011; //0; //?
+	vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA
+	//vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI
 	vgainfo.ulDDISlot2Config = 0x00130022; //0; //?
 	vgainfo.ucMemoryType = 2;
 	/* UMA Channel Number: 1 or 2. */
@@ -978,7 +976,6 @@ static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
 */
 void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
 {
-	u16 reg16;
 	u32 reg32;
 	struct southbridge_amd_rs780_config *cfg =
 	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
@@ -989,20 +986,6 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	/* GFX Core Initialization */
 	//if (port == 2) return;
 
-	/* step 1, lane reversal (only need if CMOS option is enabled) */
-	if (cfg->gfx_lane_reversal) {
-		set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
-		if (cfg->gfx_dual_slot)
-			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
-	}
-	printk(BIOS_INFO, "rs780_gfx_init step1.\n");
-
-	/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
-	/* AMD calls the configuration CrossFire */
-	if (cfg->gfx_dual_slot)
-		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
-	printk(BIOS_INFO, "rs780_gfx_init step2.\n");
-
 	/* step 2, TMDS, (only need if CMOS option is enabled) */
 	if (cfg->gfx_tmds) {
 	}
@@ -1182,9 +1165,35 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	/* Single-port/Dual-port configureation. */
 	switch (cfg->gfx_dual_slot) {
 	case 0:
-		single_port_configuration(nb_dev, dev);
+		/* step 1, lane reversal (only need if CMOS option is enabled) */
+		if (cfg->gfx_lane_reversal) {
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+		}
+		printk_info("rs780_gfx_init step1.\n");
+		printk_info("rs780_gfx_init step2.\n");
+
+		printk_info("device = %x\n", dev->path.pci.devfn >> 3);
+		if((dev->path.pci.devfn >> 3) == 2)
+			single_port_configuration(nb_dev, dev);
+		else{
+			set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
+			printk_info("If dev3.., single port. Do nothing.\n");
+		}
+
 		break;
 	case 1:
+		/* step 1, lane reversal (only need if CMOS option is enabled) */
+		if (cfg->gfx_lane_reversal) {
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+		}
+		printk_info("rs780_gfx_init step1.\n");
+		/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+		/* AMD calls the configuration CrossFire */
+		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+		printk_info("rs780_gfx_init step2.\n");
+
+		printk_info("device = %x\n", dev->path.pci.devfn >> 3);
 		dual_port_configuration(nb_dev, dev);
 		break;
 	default:
diff --git a/src/southbridge/amd/rs780/rs780_pcie.c b/src/southbridge/amd/rs780/rs780_pcie.c
index 5cea2fd650..c705614bf0 100644
--- a/src/southbridge/amd/rs780/rs780_pcie.c
+++ b/src/southbridge/amd/rs780/rs780_pcie.c
@@ -101,20 +101,6 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
 	}
 }
 
-static void pcie_init(struct device *dev)
-{
-	/* Enable pci error detecting */
-	u32 dword;
-
-	printk(BIOS_DEBUG, "pcie_init in rs780_pcie.c\n");
-
-	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1 << 8);	/* System error enable */
-	dword |= (1 << 30);	/* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
-}
-
 /**********************************************************************
 **********************************************************************/
 static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev)
@@ -249,9 +235,6 @@ void disable_pcie_bar3(device_t nb_dev)
 *****************************************/
 void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 {
-	u8 reg8;
-	u16 reg16;
-	device_t sb_dev;
 	u32 gfx_gpp_sb_sel;
 	struct southbridge_amd_rs780_config *cfg =
 	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
@@ -406,44 +389,3 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
 		switching_gpp_configurations(nb_dev, sb_dev);
 	ValidatePortEn(nb_dev);
 }
-
-/*****************************************
-* Compliant with CIM_33's PCIEMiscClkProg
-*****************************************/
-void pcie_config_misc_clk(device_t nb_dev)
-{
-	u32 reg;
-	struct bus pbus; /* fake bus for dev0 fun1 */
-
-	reg = pci_read_config32(nb_dev, 0x4c);
-	reg |= 1 << 0;
-	pci_write_config32(nb_dev, 0x4c, reg);
-
-	if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
-		/* TXCLK Clock Gating */
-		set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
-		set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
-		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
-
-		/* LCLK Clock Gating */
-		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
-		reg &= ~(1 << 16);
-		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
-	}
-
-	if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
-		/* TXCLK Clock Gating */
-		set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4);
-		set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
-		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6);
-
-		/* LCLK Clock Gating */
-		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
-		reg &= ~(1 << 24);
-		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
-	}
-
-	reg = pci_read_config32(nb_dev, 0x4c);
-	reg &= ~(1 << 0);
-	pci_write_config32(nb_dev, 0x4c, reg);
-}