southbridge/amd: add IS_ENABLED() around Kconfig symbol references

Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

4 files changed, 12 insertions, 12 deletions

diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 49ba6eb7ca..afa1affa4c 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -349,7 +349,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 void rs780_set_tom(device_t nb_dev)
 {
 	/* set TOM */
-#if CONFIG_GFXUMA
+#if IS_ENABLED(CONFIG_GFXUMA)
 	pci_write_config32(nb_dev, 0x90, uma_memory_base);
 	//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
 #else
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index b0a40be543..ec6c60236d 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -97,7 +97,7 @@ static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
 	}
 }
 /* family 10 only, for reg > 0xFF */
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
 static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos,
 		u32 mask, u32 val)
 {
@@ -143,7 +143,7 @@ static u8 is_famly10(void)
 	return (cpuid_eax(1) & 0xff00000) != 0;
 }
 
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
 static u8 l3_cache(void)
 {
 	return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
@@ -242,7 +242,7 @@ static void rs780_htinit(void)
 	} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
 		printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");
 
-		#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+		#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
 		/* HT3 mode, RPR 8.4.3 */
 		set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
 
@@ -282,7 +282,7 @@ static void rs780_htinit(void)
 	}
 }
 
-#if !CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
 /*******************************************************
 * Optimize k8 with UMA.
 * See BKDG_NPT_0F guide for details.
@@ -338,7 +338,7 @@ static void k8_optimization(void)
 #define k8_optimization() do {} while (0)
 #endif	/* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
 
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
 static void fam10_optimization(void)
 {
 	pci_devfn_t cpu_f0, cpu_f2, cpu_f3;
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 02be1f327e..7f8bcb0a3c 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -382,7 +382,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
 	/* GFX_InitFBAccess finished. */
 
-#if CONFIG_GFXUMA /* for UMA mode. */
+#if IS_ENABLED(CONFIG_GFXUMA) /* for UMA mode. */
 	/* GFX_StartMC. */
 	set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
 	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
@@ -444,7 +444,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	vgainfo.sHeader.ucTableFormatRevision = 1;
 	vgainfo.sHeader.ucTableContentRevision = 2;
 
-#if !CONFIG_GFXUMA /* SP mode. */
+#if !IS_ENABLED(CONFIG_GFXUMA) /* SP mode. */
 	// Side port support is incomplete, do not use it
 	// These parameters must match the motherboard
 	vgainfo.ulBootUpSidePortClock = 667*100;
@@ -629,7 +629,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	/* Transfer the Table to VBIOS. */
 	pointer = (u32 *)&vgainfo;
 	for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
-#if CONFIG_GFXUMA
+#if IS_ENABLED(CONFIG_GFXUMA)
 		*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
 #else
 		*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
@@ -758,7 +758,7 @@ static void rs780_internal_gfx_enable(device_t dev)
 	device_t nb_dev = dev_find_slot(0, 0);
 	msr_t sysmem;
 
-#if !CONFIG_GFXUMA
+#if !IS_ENABLED(CONFIG_GFXUMA)
 	u32 FB_Start, FB_End;
 #endif
 
@@ -801,7 +801,7 @@ static void rs780_internal_gfx_enable(device_t dev)
 	set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
 	set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
 
-#if CONFIG_GFXUMA
+#if IS_ENABLED(CONFIG_GFXUMA)
 	/* GFX_InitUMA. */
 	/* Copy CPU DDR Controller to NB MC. */
 	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index c2da54d07d..10263f25c2 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -206,7 +206,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 
 	/* Program Straps. */
 	romstrap2 = 1 << 26; // enables audio function
-#if CONFIG_GFXUMA
+#if IS_ENABLED(CONFIG_GFXUMA)
 	// bits 7-9: aperture size
 	// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
 	if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;