device: Use pcidev_on_root()

Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

4 files changed, 12 insertions, 12 deletions

diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 16270d6d89..2ef9cd6bf2 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -192,8 +192,8 @@ void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val)
 void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
 {
 	/* K8 Function1 is address map */
-	struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-	struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	struct device *k8_f1 = pcidev_on_root(0x18, 1);
+	struct device *k8_f0 = pcidev_on_root(0x18, 0);
 
 	if (in_out) {
 		u32 dword, sblk;
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 575a340894..8431223690 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -175,7 +175,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
 	CIM_STATUS Status = CIM_UNSUPPORTED;
 	u8 Bus, Dev, Reg, BusStart, BusEnd;
 	u32	Value;
-	struct device *dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev0x14 = pcidev_on_root(0x14, 4);
 	struct device *tempdev;
 	Value = pci_read_config32(dev0x14, 0x18);
 	BusStart = (Value >> 8) & 0xFF;
@@ -235,7 +235,7 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
 	int i, j, n = 7;
 	struct device *k8_f1;
 
-	k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	k8_f1 = pcidev_on_root(0x18, 1);
 
 	for (i = 0; i < 8; i++) {
 		int k = 0, MmioReg;
@@ -787,7 +787,7 @@ static void rs780_internal_gfx_enable(struct device *dev)
 
 	/* LPC DMA Deadlock workaround? */
 	/* GFX_InitCommon*/
-	struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	struct device *k8_f0 = pcidev_on_root(0x18, 0);
 	l_dword = pci_read_config32(k8_f0, 0x68);
 	l_dword &= ~(3 << 21);
 	l_dword |= (1 << 21);
@@ -802,9 +802,9 @@ static void rs780_internal_gfx_enable(struct device *dev)
 #if IS_ENABLED(CONFIG_GFXUMA)
 	/* GFX_InitUMA. */
 	/* Copy CPU DDR Controller to NB MC. */
-	struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-	struct device *k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	struct device *k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
+	struct device *k8_f1 = pcidev_on_root(0x18, 1);
+	struct device *k8_f2 = pcidev_on_root(0x18, 2);
+	struct device *k8_f4 = pcidev_on_root(0x18, 4);
 	for (i = 0; i < 12; i++) {
 		l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
 		nbmc_write_index(nb_dev, 0x30 + i, l_dword);
@@ -1145,7 +1145,7 @@ static void dynamic_link_width_control(struct device *nb_dev, struct device *dev
 	while (reg32 & 0x100);
 
 	/* step 5.9.1.6 */
-	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	sb_dev = pcidev_on_root(8, 0);
 	do {
 		reg32 = pci_ext_read_config32(nb_dev, sb_dev,
 					  PCIE_VC0_RESOURCE_STATUS);
diff --git a/src/southbridge/amd/rs780/ht.c b/src/southbridge/amd/rs780/ht.c
index 43fb899803..94df2337c1 100644
--- a/src/southbridge/amd/rs780/ht.c
+++ b/src/southbridge/amd/rs780/ht.c
@@ -26,7 +26,7 @@ void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev)
 	struct device *cpu_f0;
 	u8 reg;
 
-	cpu_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	cpu_f0 = pcidev_on_root(0x18, 0);
 	set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21);
 
 	reg = nbpcie_p_read_index(sb_dev, 0x10);
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index a753da77be..c5e38c130c 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -271,14 +271,14 @@ void rs780_enable(struct device *dev)
 
 	printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
 
-	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	nb_dev = pcidev_on_root(0, 0);
 	if (!nb_dev) {
 		die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n");
 		/* NOT REACHED */
 	}
 
 	/* sb_dev (dev 8) is a bridge that links to southbridge. */
-	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	sb_dev = pcidev_on_root(8, 0);
 	if (!sb_dev) {
 		die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n");
 		/* NOT REACHED */