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| author | Myles Watson <mylesgw@gmail.com> | 2010-03-22 16:33:25 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-03-22 16:33:25 +0000 |
| commit | 08e0fb881093c977488de6e8d701dd69369123ec (patch) | |
| tree | 5a7d8aa8415a0b2143ed6f4d52af87191a33561c /src/southbridge/amd/rs780 | |
| parent | 53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72 (diff) | |
| download | coreboot-08e0fb881093c977488de6e8d701dd69369123ec.tar.xz | |
Fix all the format string warnings.
Some other random warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/rs780')
| -rw-r--r-- | src/southbridge/amd/rs780/rs780_pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs780/rs780_pcie.c b/src/southbridge/amd/rs780/rs780_pcie.c index 186266b8f1..5cea2fd650 100644 --- a/src/southbridge/amd/rs780/rs780_pcie.c +++ b/src/southbridge/amd/rs780/rs780_pcie.c @@ -255,7 +255,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) u32 gfx_gpp_sb_sel; struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port); + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev->path.pci.devfn, dev->path.pci.devfn, port); gfx_gpp_sb_sel = port >= 4 && port <= 8 ? PCIE_CORE_INDEX_GPPSB : /* 4,5,6,7,8 */ |