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authorZheng Bao <zheng.bao@amd.com>2010-03-16 01:41:14 +0000
committerZheng Bao <Zheng.Bao@amd.com>2010-03-16 01:41:14 +0000
commit1088bbff4503df7e8507aae45da823268262ca8f (patch)
tree414123cac2bdd5f70b10d64082b792e7a52e2c45 /src/southbridge/amd/rs780
parenteff2ffdee8489f97b265b0335b766be3db9a633a (diff)
downloadcoreboot-1088bbff4503df7e8507aae45da823268262ca8f.tar.xz
Features supported in RS780 code:
* PCIe initialization. * Internal Graphics initialization. * HT Link initialization. It works in HT1 or HT3 mode. Note: 1. I tried to add the description of every step to the code. For example, if it is made based on rpr, section 2.4.5, I will pasted the words from 2.4.5 to the c code. But the document I worked with might be different with the most updated one. A new section has been added and the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I correct every comment if I met one. But I have to confess that I am so reluctant to find out everyone. I believe it will be correct in the long run. 2. The interanl graphics part is done by Libo Feng <libo.feng@amd.com>. 3. There is a conflict between RPR and our CIM code. Please see the comment in switching_gppsb_configurations in rs780_pcie.c. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/rs780')
-rw-r--r--src/southbridge/amd/rs780/Config.lb27
-rw-r--r--src/southbridge/amd/rs780/Kconfig22
-rw-r--r--src/southbridge/amd/rs780/Makefile.inc5
-rw-r--r--src/southbridge/amd/rs780/chip.h40
-rw-r--r--src/southbridge/amd/rs780/rs780.c356
-rw-r--r--src/southbridge/amd/rs780/rs780.h211
-rw-r--r--src/southbridge/amd/rs780/rs780_cmn.c353
-rw-r--r--src/southbridge/amd/rs780/rs780_early_setup.c668
-rw-r--r--src/southbridge/amd/rs780/rs780_gfx.c1194
-rw-r--r--src/southbridge/amd/rs780/rs780_ht.c90
-rw-r--r--src/southbridge/amd/rs780/rs780_pcie.c449
-rw-r--r--src/southbridge/amd/rs780/rs780_rev.h27
12 files changed, 3442 insertions, 0 deletions
diff --git a/src/southbridge/amd/rs780/Config.lb b/src/southbridge/amd/rs780/Config.lb
new file mode 100644
index 0000000000..56b3dea059
--- /dev/null
+++ b/src/southbridge/amd/rs780/Config.lb
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+##
+##
+
+config chip.h
+driver rs780_cmn.o
+driver rs780.o
+driver rs780_pcie.o
+driver rs780_ht.o
+driver rs780_gfx.o
diff --git a/src/southbridge/amd/rs780/Kconfig b/src/southbridge/amd/rs780/Kconfig
new file mode 100644
index 0000000000..ed7c9de8a7
--- /dev/null
+++ b/src/southbridge/amd/rs780/Kconfig
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_AMD_RS780
+ bool
+
diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc
new file mode 100644
index 0000000000..3d6fad10e3
--- /dev/null
+++ b/src/southbridge/amd/rs780/Makefile.inc
@@ -0,0 +1,5 @@
+driver-y += rs780.o
+driver-y += rs780_cmn.o
+driver-y += rs780_pcie.o
+driver-y += rs780_ht.o
+driver-y += rs780_gfx.o
diff --git a/src/southbridge/amd/rs780/chip.h b/src/southbridge/amd/rs780/chip.h
new file mode 100644
index 0000000000..fa72a01e31
--- /dev/null
+++ b/src/southbridge/amd/rs780/chip.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef RS780_CHIP_H
+#define RS780_CHIP_H
+
+/* Member variables are defined in Config.lb. */
+struct southbridge_amd_rs780_config
+{
+ u8 gppsb_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
+ u8 gpp_configuration; /* The configuration of General Purpose Port, C/D. */
+ u16 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
+ u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */
+ u8 gfx_dual_slot; /* Is it dual graphics slots */
+ u8 gfx_lane_reversal; /* Single/Dual slot lan reversal */
+ u8 gfx_tmds; /* whether support TMDS? */
+ u8 gfx_compliance; /* whether support compliance? */
+ u8 gfx_reconfiguration; /* Dynamic Lind Width Control */
+ u8 gfx_link_width; /* Desired width of lane 2 */
+};
+struct chip_operations;
+extern struct chip_operations southbridge_amd_rs780_ops;
+
+#endif /* RS780_CHIP_H */
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
new file mode 100644
index 0000000000..b7ec1154ce
--- /dev/null
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -0,0 +1,356 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include "rs780.h"
+
+/*****************************************
+* rs780_config_misc_clk()
+*****************************************/
+void static rs780_config_misc_clk(device_t nb_dev)
+{
+ u32 reg;
+ u16 word;
+ u8 byte;
+ struct bus pbus; /* fake bus for dev0 fun1 */
+
+ reg = pci_read_config32(nb_dev, 0x4c);
+ reg |= 1 << 0;
+ pci_write_config32(nb_dev, 0x4c, reg);
+
+ word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
+ word &= 0xf00;
+ pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
+
+ word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
+ word &= ~((1 << 12) | (1 << 13) | (1 << 14));
+ word |= 1 << 13;
+ pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
+
+ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
+ pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+
+ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+ reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
+ reg |= 1 << 13;
+ pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+
+ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg |= 1 << 24;
+ pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+
+ reg = nbmc_read_index(nb_dev, 0x7a);
+ reg &= ~0x3f;
+ reg |= 1 << 2;
+ reg &= ~(1 << 6);
+ set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
+ nbmc_write_index(nb_dev, 0x7a, reg);
+ /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
+ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg &= ~(1 << 23);
+ reg |= 1 << 24;
+ pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+
+ /* Programming NB CLK table. */
+ byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0);
+ byte |= 0x01;
+ pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, byte);
+
+#if 0
+ /* Powerdown reference clock to graphics core PLL in northbridge only mode */
+ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+ reg |= 1 << 21;
+ pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+
+ /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
+ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg |= (1 << 23) | (1 << 24);
+ pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+
+ /* Powerdown clock to memory controller in northbridge only mode */
+ byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
+ byte |= 1 << 0;
+ pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
+
+ /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */
+ /* TODO: */
+#endif
+
+ reg = pci_read_config32(nb_dev, 0x4c);
+ reg &= ~(1 << 0);
+ pci_write_config32(nb_dev, 0x4c, reg);
+
+ set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
+}
+
+u32 get_vid_did(device_t dev)
+{
+ return pci_read_config32(dev, 0);
+}
+
+void rs780_nb_pci_table(device_t nb_dev)
+{ /* NBPOR_InitPOR function. */
+ u8 temp8;
+ u16 temp16;
+ u32 temp32;
+
+ /* Program NB PCI table. */
+ temp16 = pci_read_config16(nb_dev, 0x04);
+ printk_debug("NB_PCI_REG04 = %x.\n", temp16);
+ temp32 = pci_read_config32(nb_dev, 0x84);
+ printk_debug("NB_PCI_REG84 = %x.\n", temp32);
+
+ pci_write_config8(nb_dev, 0x4c, 0x42);
+
+ temp8 = pci_read_config8(nb_dev, 0x4e);
+ temp8 |= 0x05;
+ pci_write_config8(nb_dev, 0x4e, temp8);
+
+ temp32 = pci_read_config32(nb_dev, 0x4c);
+ printk_debug("NB_PCI_REG4C = %x.\n", temp32);
+
+ /* disable GFX debug. */
+ temp8 = pci_read_config8(nb_dev, 0x8d);
+ temp8 &= ~(1<<1);
+ pci_write_config8(nb_dev, 0x8d, temp8);
+
+ /* set temporary NB TOM to 0x40000000. */
+ rs780_set_tom(nb_dev);
+
+ /* Program NB HTIU table. */
+#if 0
+ set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9);
+ set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202);
+ set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001);
+ set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27);
+ set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000);
+ set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11);
+ set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3);
+ set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1);
+ set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30);
+ set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31));
+ set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10);
+ set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28);
+
+ /* Program NB MISC table. */
+ set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180);
+ set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106);
+ set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100);
+ set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100);
+ set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100);
+ set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100);
+ set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100);
+ set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100);
+ set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100);
+ set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100);
+ set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0);
+ set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0);
+ set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5);
+ set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10);
+ set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10);
+ set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25);
+ set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24);
+ set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28);
+ set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13);
+ set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10);
+ set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30);
+ set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0);
+ set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0);
+ set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17);
+ set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23);
+ set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22);
+ set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48);
+
+ /* the last two step. */
+ set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8);
+ set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4);
+#endif
+}
+
+void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
+{
+ /* NB_InitGFXStraps */
+ u32 MMIOBase, apc04, apc18, apc24;
+ volatile u32 * strap;
+
+ /* Get PCIe configuration space. */
+ MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;
+ /* Temporarily disable PCIe configuration space. */
+ set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0);
+
+ set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7);
+ /* Set a temporary Bus number. */
+ apc18 = pci_read_config32(dev, 0x18);
+ pci_write_config32(dev, 0x18, 0x010100);
+ /* Set MMIO for AGP target(graphics controller). base = 0xe0000000, limit = 0x20000 */
+ apc24 = pci_read_config32(dev, 0x24);
+ pci_write_config32(dev, 0x24, (MMIOBase>>16)+((MMIOBase+0x20000)&0xffff0000));
+ /* Enable memory access. */
+ apc04 = pci_read_config32(dev, 0x04);
+ pci_write_config8(dev, 0x04, 0x02);
+
+ /* Program Straps. */
+ strap = MMIOBase + 0x15020;
+#if (CONFIG_GFXUMA == 1)
+ *strap = 1<<7; /* the format of BIF_MEM_AP_SIZE. 001->256MB? */
+#else
+ *strap = 0; /* 128M SP memory, 000 -> 128MB */
+#endif
+ strap = MMIOBase + 0x15000;
+ *strap = 0x2c006300;
+ strap = MMIOBase + 0x15010;
+ *strap = 0x03015330;
+ //strap = MMIOBase + 0x15020;
+ //*strap |= 0x00000040; /* Disable HDA device. */
+ strap = MMIOBase + 0x15030;
+ *strap = 0x00001002;
+ strap = MMIOBase + 0x15040;
+ *strap = 0x00000000;
+ strap = MMIOBase + 0x15050;
+ *strap = 0x00000000;
+ strap = MMIOBase + 0x15220;
+ *strap = 0x03c03800;
+ strap = MMIOBase + 0x15060;
+ *strap = 0x00000000;
+
+ /* BIF switches into normal functional mode. */
+ set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<4 | 1<<5, 1<<5);
+
+ /* NB Revision is A12. */
+ set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9);
+
+ /* Restore APC04, APC18, APC24. */
+ pci_write_config32(dev, 0x04, apc04);
+ pci_write_config32(dev, 0x18, apc18);
+ pci_write_config32(dev, 0x24, apc24);
+
+ /* Enable PCIe configuration space. */
+ set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28);
+ printk_info("GC is accessible from now on.\n");
+}
+
+/***********************************************
+* 0:00.0 NBCFG :
+* 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default
+* 0:01.0 P2P Internal:
+* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
+* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
+* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
+* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
+* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
+* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
+* 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1
+* case 0 will be called twice, one is by cpu in hypertransport.c line458,
+* the other is by rs780.
+***********************************************/
+void rs780_enable(device_t dev)
+{
+ device_t nb_dev = 0, sb_dev = 0;
+ int dev_ind;
+
+ printk_info("rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
+
+ nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (!nb_dev) {
+ die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n");
+ /* NOT REACHED */
+ }
+
+ /* sb_dev (dev 8) is a bridge that links to southbridge. */
+ sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+ if (!sb_dev) {
+ die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n");
+ /* NOT REACHED */
+ }
+
+ dev_ind = dev->path.pci.devfn >> 3;
+ switch (dev_ind) {
+ case 0: /* bus0, dev0, fun0; */
+ printk_info("Bus-0, Dev-0, Fun-0.\n");
+ enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
+ config_gpp_core(nb_dev, sb_dev);
+ rs780_gpp_sb_init(nb_dev, sb_dev, 8);
+ /* 5.10.8.4. set SB payload size: 64byte */
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11);
+
+ /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */
+ rs780_config_misc_clk(nb_dev);
+
+ rs780_nb_pci_table(nb_dev);
+ break;
+
+ case 1: /* bus0, dev1, APC. */
+ printk_info("Bus-0, Dev-1, Fun-0.\n");
+ rs780_nb_gfx_dev_table(nb_dev, dev);
+ break;
+ case 2: /* bus0, dev2,3, two GFX */
+ case 3:
+ printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
+ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
+ (dev->enabled ? 0 : 1) << dev_ind);
+ if (dev->enabled)
+ rs780_gfx_init(nb_dev, dev, dev_ind);
+ break;
+ case 4: /* bus0, dev4-7, four GPPSB */
+ case 5:
+ case 6:
+ case 7:
+ printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
+ dev->enabled);
+ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
+ (dev->enabled ? 0 : 1) << dev_ind);
+ if (dev->enabled)
+ rs780_gpp_sb_init(nb_dev, dev, dev_ind);
+ break;
+ case 8: /* bus0, dev8, SB */
+ printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
+ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
+ (dev->enabled ? 1 : 0) << 6);
+ if (dev->enabled)
+ rs780_gpp_sb_init(nb_dev, dev, dev_ind);
+ disable_pcie_bar3(nb_dev);
+ break;
+ case 9: /* bus 0, dev 9,10, GPP */
+ case 10:
+ printk_info("Bus-0, Dev-9, 10, Fun-0. enable=%d\n",
+ dev->enabled);
+ enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
+ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
+ (dev->enabled ? 0 : 1) << (7 + dev_ind));
+ if (dev->enabled)
+ rs780_gpp_sb_init(nb_dev, dev, dev_ind);
+ /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */
+ break;
+ default:
+ printk_debug("unknown dev: %s\n", dev_path(dev));
+ }
+}
+
+struct chip_operations southbridge_amd_rs780_ops = {
+ CHIP_NAME("ATI RS780")
+ .enable_dev = rs780_enable,
+};
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
new file mode 100644
index 0000000000..7939303fe1
--- /dev/null
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -0,0 +1,211 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __RS780_H__
+#define __RS780_H__
+
+#include <stdint.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+#include "rs780_rev.h"
+
+#define NBMISC_INDEX 0x60
+#define NBHTIU_INDEX 0x94
+#define NBMC_INDEX 0xE8
+#define NBPCIE_INDEX 0xE0
+#define EXT_CONF_BASE_ADDRESS 0xE0000000
+#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
+
+#define get_nb_rev(dev) pci_read_config8((dev), 0x89)
+
+typedef struct __PCIE_CFG__ {
+ u16 Config;
+ u8 ResetReleaseDelay;
+ u8 Gfx0Width;
+ u8 Gfx1Width;
+ u8 GfxPayload;
+ u8 GppPayload;
+ u16 PortDetect;
+ u8 PortHp; /* hot plug */
+ u16 DbgConfig;
+ u32 DbgConfig2;
+ u8 GfxLx;
+ u8 GppLx;
+ u8 NBSBLx;
+ u8 PortSlotInit;
+ u8 Gfx0Pwr;
+ u8 Gfx1Pwr;
+ u8 GppPwr;
+} PCIE_CFG;
+
+/* The Integrated Info Table */
+#define USHORT u16
+#define UCHAR u8
+#define ULONG u32
+
+typedef struct _ATOM_COMMON_TABLE_HEADER
+{
+ USHORT usStructureSize;
+ UCHAR ucTableFormatRevision;
+ UCHAR ucTableContentRevision;
+}ATOM_COMMON_TABLE_HEADER;
+
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulBootUpEngineClock; //in 10kHz unit
+ ULONG ulReserved1[2]; //must be 0x0 for the reserved
+ ULONG ulBootUpUMAClock; //in 10kHz unit
+ ULONG ulBootUpSidePortClock; //in 10kHz unit
+ ULONG ulMinSidePortClock; //in 10kHz unit
+ ULONG ulReserved2[6]; //must be 0x0 for the reserved
+ ULONG ulSystemConfig;
+//[0]=1: PowerExpress mode
+// =0 Non-PowerExpress mode;
+//[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will disable other power state in VBIOS table.
+// =0: system boots up at driver control state. Power state depends on VBIOS PP table.
+//[2]=1: PWM method is used on NB voltage control.
+// =0: GPIO method is used.
+//[3]=1: Only one power state(Performance) will be supported.
+// =0: Number of power states supported is from VBIOS PP table.
+//[4]=1: CLMC is supported and enabled on current system.
+// =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
+//[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
+// =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
+//[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and VBIOS PP table voltage drop/throttling request will be ignored.
+// =0: Voltage settings is determined by VBIOS PP table.
+//[7]=1: Enable CLMC Hybird Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
+// =0: Enable regular CLMC mode, CDLD and CILR will be enabled.
+//[8]=1: CDLF is supported and enabled by fuse //CHP 914
+// =0: CDLF is not supported and not enabled by fuses
+ ULONG ulBootUpReqDisplayVector;
+ ULONG ulOtherDisplayMisc;
+ ULONG ulDDISlot1Config;
+ ULONG ulDDISlot2Config;
+ UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
+ UCHAR ucUMAChannelNumber;
+ UCHAR ucDockingPinBit;
+ UCHAR ucDockingPinPolarity;
+ ULONG ulDockingPinCFGInfo;
+ ULONG ulCPUCapInfo;
+ USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform
+ // 1 - non inverted waveform
+ USHORT usMaxNBVoltage;
+ USHORT usMinNBVoltage;
+ USHORT usBootUpNBVoltage;
+ ULONG ulHTLinkFreq; //in 10Khz
+ USHORT usMinHTLinkWidth; // if no CLMC, usMinHTLinkWidth should be equal to usMaxHTLinkWidth??
+ USHORT usMaxHTLinkWidth;
+ USHORT usUMASyncStartDelay; // will be same as usK8SyncStartDelay on RS690
+ USHORT usUMADataReturnTime; // will be same as usK8DataReturnTime on RS690
+ USHORT usLinkStatusZeroTime;
+ USHORT usReserved;
+ ULONG ulHighVoltageHTLinkFreq; // in 10Khz
+ ULONG ulLowVoltageHTLinkFreq; // in 10Khz
+ USHORT usMaxUpStreamHTLinkWidth;
+ USHORT usMaxDownStreamHTLinkWidth;
+ USHORT usMinUpStreamHTLinkWidth;
+ USHORT usMinDownStreamHTLinkWidth;
+ ULONG ulReserved3[97]; //must be 0x0
+} ATOM_INTEGRATED_SYSTEM_INFO_V2;
+
+/* PCIE config flags */
+#define PCIE_DUALSLOT_CONFIG (1 << 0)
+#define PCIE_OVERCLOCK_ENABLE (1 << 1)
+#define PCIE_GPP_CLK_GATING (1 << 2)
+#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3)
+#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4)
+#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5)
+#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7)
+#define PCIE_GFX_CLK_GATING (1 << 11)
+#define PCIE_GFX_COMPLIANCE (1 << 14)
+#define PCIE_GPP_COMPLIANCE (1 << 15)
+
+/* -------------------- ----------------------
+* NBMISCIND
+ ------------------- -----------------------*/
+#define PCIE_LINK_CFG 0x8
+#define PCIE_NBCFG_REG7 0x37
+#define STRAPS_OUTPUT_MUX_7 0x67
+#define STRAPS_OUTPUT_MUX_A 0x6a
+
+/* -------------------- ----------------------
+* PCIEIND
+ ------------------- -----------------------*/
+#define PCIE_CI_CNTL 0x20
+#define PCIE_LC_LINK_WIDTH 0xa2
+#define PCIE_LC_STATE0 0xa5
+#define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */
+
+#define PCIE_CORE_INDEX_GFX (0x00 << 16) /* see 5.2.2 */
+#define PCIE_CORE_INDEX_GPPSB (0x01 << 16)
+#define PCIE_CORE_INDEX_GPP (0x02 << 16)
+#define PCIE_CORE_INDEX_BRDCST (0x03 << 16)
+
+/* contents of PCIE_NBCFG_REG7 */
+#define RECONFIG_GPPSB_EN (1 << 12)
+#define RECONFIG_GPPSB_GPPSB (1 << 14)
+#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15)
+#define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17)
+
+/* contents of PCIE_VC0_RESOURCE_STATUS */
+#define VC_NEGOTIATION_PENDING (1 << 1)
+
+#define LC_STATE_RECONFIG_GPPSB 0x10
+
+/* ------------------------------------------------
+* Global variable
+* ------------------------------------------------- */
+extern PCIE_CFG AtiPcieCfg;
+
+/* ----------------- export funtions ----------------- */
+u32 nbmisc_read_index(device_t nb_dev, u32 index);
+void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);
+u32 nbpcie_p_read_index(device_t dev, u32 index);
+void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
+u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
+void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
+u32 htiu_read_index(device_t nb_dev, u32 index);
+void htiu_write_index(device_t nb_dev, u32 index, u32 data);
+u32 nbmc_read_index(device_t nb_dev, u32 index);
+void nbmc_write_index(device_t nb_dev, u32 index, u32 data);
+
+u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
+void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
+
+void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val);
+void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val);
+void rs780_set_tom(device_t nb_dev);
+
+void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
+void enable_pcie_bar3(device_t nb_dev);
+void disable_pcie_bar3(device_t nb_dev);
+
+void rs780_enable(device_t dev);
+void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
+void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port);
+void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
+void config_gpp_core(device_t nb_dev, device_t sb_dev);
+void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
+u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
+#endif /* RS780_H */
diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/rs780_cmn.c
new file mode 100644
index 0000000000..9b6ccf627d
--- /dev/null
+++ b/src/southbridge/amd/rs780/rs780_cmn.c
@@ -0,0 +1,353 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <boot/coreboot_tables.h>
+#include <delay.h>
+#include "rs780.h"
+
+static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+{
+ pci_write_config32(dev, index_reg, index);
+ return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+ pci_write_config32(dev, index_reg, index);
+ pci_write_config32(dev, index_reg + 0x4, data);
+}
+
+/* extension registers */
+u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
+{
+ /*get BAR3 base address for nbcfg0x1c */
+ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+ printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+ dev->path.pci.devfn);
+ addr |= dev->bus->secondary << 20 | /* bus num */
+ dev->path.pci.devfn << 12 | reg;
+ return *((u32 *) addr);
+}
+
+void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+
+ /*get BAR3 base address for nbcfg0x1c */
+ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+ /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+ dev->path.pci.devfn);*/
+ addr |= dev->bus->secondary << 20 | /* bus num */
+ dev->path.pci.devfn << 12 | reg_pos;
+
+ reg = reg_old = *((u32 *) addr);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ *((u32 *) addr) = val;
+ }
+}
+
+u32 nbmisc_read_index(device_t nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+u32 nbpcie_p_read_index(device_t dev, u32 index)
+{
+ return nb_read_index((dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
+{
+ nb_write_index((dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 htiu_read_index(device_t nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+u32 nbmc_read_index(device_t nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ pci_write_config32(nb_dev, reg_pos, reg);
+ }
+}
+
+void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
+{
+ u8 reg_old, reg;
+ reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ pci_write_config8(nb_dev, reg_pos, reg);
+ }
+}
+
+void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ nbmc_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ htiu_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ nbmisc_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
+ }
+}
+
+/***********************************************************
+* To access bar3 we need to program PCI MMIO 7 in K8.
+* in_out:
+* 1: enable/enter k8 temp mmio base
+* 0: disable/restore
+***********************************************************/
+void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
+{
+ /* K8 Function1 is address map */
+ device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+
+ if (in_out) {
+ pci_write_config32(k8_f1, 0xbc,
+ (((pcie_base_add + 0x10000000 -
+ 1) >> 8) & 0xffffff00) | 0x8);
+ pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
+ pci_write_config32(k8_f1, 0xb4,
+ ((mmio_base_add + 0x10000000 -
+ 1) >> 8) & 0xffffff00);
+ pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
+ } else {
+ pci_write_config32(k8_f1, 0xb8, 0);
+ pci_write_config32(k8_f1, 0xbc, 0);
+ pci_write_config32(k8_f1, 0xb0, 0);
+ pci_write_config32(k8_f1, 0xb4, 0);
+ }
+}
+
+void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
+{
+ switch (port) {
+ case 2: /* GFX, bit4-5 */
+ case 3:
+ set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+ 1 << (port + 2), 0 << (port + 2));
+ break;
+ case 4: /* GPPSB, bit20-24 */
+ case 5:
+ case 6:
+ case 7:
+ set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+ 1 << (port + 17), 0 << (port + 17));
+ break;
+ case 9: /* GPP, bit 4,5 of miscind 0x2D */
+ case 10:
+ set_nbmisc_enable_bits(nb_dev, 0x2D,
+ 1 << (port - 5), 0 << (port - 5));
+ break;
+ }
+}
+
+/********************************************************************************************************
+* Output:
+* 0: no device is present.
+* 1: device is present and is trained.
+********************************************************************************************************/
+u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
+{
+ u16 count = 5000;
+ u32 lc_state, reg, current_link_width, lane_mask;
+ int8_t current, res = 0;
+ u32 gfx_gpp_sb_sel;
+ void set_pcie_dereset();
+ void set_pcie_reset();
+
+ switch (port) {
+ case 2 ... 3:
+ gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX;
+ break;
+ case 4 ... 7:
+ gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPPSB;
+ break;
+ case 9 ... 10:
+ gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP;
+ break;
+ }
+
+ while (count--) {
+ mdelay(40);
+ udelay(200);
+ lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */
+ printk_debug("PcieLinkTraining port=%x:lc current state=%x\n",
+ port, lc_state);
+ current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */
+
+ switch (current) {
+ case 0x00: /* 0x00-0x04 means no device is present */
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x04:
+ res = 0;
+ count = 0;
+ break;
+ case 0x06:
+ /* read back current link width [6:4]. */
+ current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7;
+ /* 4 means 7:4 and 15:12
+ * 3 means 7:2 and 15:10
+ * 2 means 7:1 and 15:9
+ * egnoring the reversal case
+ */
+ lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
+ reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel);
+ reg |= lane_mask << 8 | lane_mask;
+ reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */
+ nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg);
+ printk_debug("link_width=%x, lane_mask=%x",
+ current_link_width, lane_mask);
+ set_pcie_reset();
+ mdelay(1);
+ set_pcie_dereset();
+ break;
+ case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */
+ res = 0;
+ count = 0;
+ break;
+ case 0x10:
+ reg =
+ pci_ext_read_config32(nb_dev, dev,
+ PCIE_VC0_RESOURCE_STATUS);
+ printk_debug("PcieTrainPort reg=0x%x\n", reg);
+ /* check bit1 */
+ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
+ /* set bit8=1, bit0-2=bit4-6 */
+ u32 tmp;
+ reg =
+ nbpcie_p_read_index(dev,
+ PCIE_LC_LINK_WIDTH);
+ tmp = (reg >> 4) && 0x3; /* get bit4-6 */
+ reg &= 0xfff8; /* clear bit0-2 */
+ reg += tmp; /* merge */
+ reg |= 1 << 8;
+ count++; /* CIM said "keep in loop"? */
+ } else {
+ res = 1;
+ count = 0;
+ }
+ break;
+ default: /* reset pcie */
+ res = 0;
+ count = 0; /* break loop */
+ break;
+ }
+ }
+ return res;
+}
+
+/*
+* Compliant with CIM_33's ATINB_SetToms.
+* Set Top Of Memory below and above 4G.
+*/
+void rs780_set_tom(device_t nb_dev)
+{
+ extern uint64_t uma_memory_base;
+
+ /* set TOM */
+ pci_write_config32(nb_dev, 0x90, uma_memory_base);
+ //nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
+}
+
diff --git a/src/southbridge/amd/rs780/rs780_early_setup.c b/src/southbridge/amd/rs780/rs780_early_setup.c
new file mode 100644
index 0000000000..7811f0bde6
--- /dev/null
+++ b/src/southbridge/amd/rs780/rs780_early_setup.c
@@ -0,0 +1,668 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "rs780_rev.h"
+
+#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
+#define NBMISC_INDEX 0x60
+#define NBMC_INDEX 0xE8
+
+static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+{
+ pci_write_config32(dev, index_reg, index);
+ return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+ pci_write_config32(dev, index_reg, index /* | 0x80 */ );
+ pci_write_config32(dev, index_reg + 0x4, data);
+}
+
+static u32 nbmisc_read_index(device_t nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+static u32 htiu_read_index(device_t nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+static void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+static u32 nbmc_read_index(device_t nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+static void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+ u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ htiu_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+ u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ nbmisc_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+ u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ pci_write_config32(nb_dev, reg_pos, reg);
+ }
+}
+/* family 10 only, for reg > 0xFF */
+#if CONFIG_CAR_FAM10 == 1
+static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
+ u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = Get_NB32(fam10_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ Set_NB32(fam10_dev, reg_pos, reg);
+ }
+}
+#else
+#define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0)
+#endif
+
+
+static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
+ u8 val)
+{
+ u8 reg_old, reg;
+ reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ pci_write_config8(nb_dev, reg_pos, reg);
+ }
+}
+
+static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+ u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ nbmc_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+static void get_cpu_rev()
+{
+ u32 eax;
+
+ eax = cpuid_eax(1);
+ printk_info("get_cpu_rev EAX=0x%x.\n", eax);
+ if (eax <= 0xfff)
+ printk_info("CPU Rev is K8_Cx.\n");
+ else if (eax <= 0x10fff)
+ printk_info("CPU Rev is K8_Dx.\n");
+ else if (eax <= 0x20fff)
+ printk_info("CPU Rev is K8_Ex.\n");
+ else if (eax <= 0x40fff)
+ printk_info("CPU Rev is K8_Fx.\n");
+ else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */
+ printk_info("CPU Rev is K8_G1.\n");
+ else if (eax <= 0X60FF0)
+ printk_info("CPU Rev is K8_G0.\n");
+ else if (eax <= 0x100000)
+ printk_info("CPU Rev is K8_G1.\n");
+ else if (eax <= 0x100f00)
+ printk_info("CPU Rev is Fam 10.\n");
+ else
+ printk_info("CPU Rev is K8_10.\n");
+}
+
+static u8 is_famly10()
+{
+ return (cpuid_eax(1) & 0xff00000) != 0;
+}
+
+static u8 l3_cache()
+{
+ return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
+}
+
+static u8 cpu_core_number()
+{
+ return (cpuid_ecx(0x80000008) & 0xFF) + 1;
+}
+
+static u8 get_nb_rev(device_t nb_dev)
+{
+ u8 reg;
+ reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */
+ switch(reg & 3)
+ {
+ case 0x01:
+ reg = REV_RS780_A12;
+ break;
+ case 0x02:
+ reg = REV_RS780_A13;
+ break;
+ default:
+ reg = REV_RS780_A11;
+ break;
+ }
+ return reg;
+}
+
+/*****************************************
+ * Init HT link speed/width for rs780 -- k8 link
+ * 1: Check CPU Family, Family10?
+ * 2: Get CPU's HT speed and width
+ * 3: Decide HT mode 1 or 3 by HT Speed. >1GHz: HT3, else HT1
+ *****************************************/
+static const u8 rs780_ibias[] = {
+ /* 1, 3 are reserved. */
+ [0x0] = 0x4C, /* 200Mhz HyperTransport 1 only */
+ [0x2] = 0x4C, /* 400Mhz HyperTransport 1 only */
+ [0x4] = 0xB6, /* 600Mhz HyperTransport 1 only */
+ [0x5] = 0x4C, /* 800Mhz HyperTransport 1 only */
+ [0x6] = 0x9D, /* 1Ghz HyperTransport 1 only */
+ /* HT3 for Family 10 */
+ [0x7] = 0xB6, /* 1.2Ghz HyperTransport 3 only */
+ [0x8] = 0x2B, /* 1.4Ghz HyperTransport 3 only */
+ [0x9] = 0x4C, /* 1.6Ghz HyperTransport 3 only */
+ [0xa] = 0x6C, /* 1.8Ghz HyperTransport 3 only */
+ [0xb] = 0x9D, /* 2.0Ghz HyperTransport 3 only */
+ [0xc] = 0xAD, /* 2.2Ghz HyperTransport 3 only */
+ [0xd] = 0xB6, /* 2.4Ghz HyperTransport 3 only */
+ [0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */
+};
+
+static void rs780_htinit()
+{
+ /*
+ * About HT, it has been done in enumerate_ht_chain().
+ */
+ device_t cpu_f0, rs780_f0, clk_f1;
+ u32 reg;
+ u8 cpu_ht_freq, ibias;
+
+ cpu_f0 = PCI_DEV(0, 0x18, 0);
+ /************************
+ * get cpu's ht freq, in cpu's function 0, offset 0x88
+ * bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
+ * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
+ * value to this reg, and that value takes effect on the next warm reset or
+ * LDTSTOP_L disconnect sequence.
+ * please see the table rs780_ibias about the value and its corresponding frequency.
+ ************************/
+ reg = pci_read_config32(cpu_f0, 0x88);
+ cpu_ht_freq = (reg & 0xf00) >> 8;
+ printk_info("rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
+ rs780_f0 = PCI_DEV(0, 0, 0);
+ //set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28);
+
+ clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */
+
+ ibias = rs780_ibias[cpu_ht_freq];
+
+ /* If HT freq>1GHz, we assume the CPU is fam10, else it is K8.
+ * Is it appropriate?
+ * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases.
+ * So we check 6 only, it would be faster. */
+ if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) ||
+ (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) {
+ printk_info("rs780_htinit: HT1 mode\n");
+
+ /* HT1 mode, RPR 8.4.2 */
+ /* set IBIAS code */
+ set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
+ /* Optimizes chipset HT transmitter drive strength */
+ set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
+ } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
+ printk_info("rs780_htinit: HT3 mode\n");
+
+ #if CONFIG_CAR_FAM10 == 1 /* save some spaces */
+ /* HT3 mode, RPR 8.4.3 */
+ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
+
+ /* set IBIAS code */
+ set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
+ /* Optimizes chipset HT transmitter drive strength */
+ set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
+ /* Enables error-retry mode */
+ set_nbcfg_enable_bits(rs780_f0, 0x44, 0x1, 0x1);
+ /* Enables scrambling and Disalbes command throttling */
+ set_nbcfg_enable_bits(rs780_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14));
+ /* Enables transmitter de-emphasis */
+ set_nbcfg_enable_bits(rs780_f0, 0xa4, 1 << 31, 1 << 31);
+ /* Enabels transmitter de-emphasis level */
+ /* Sets training 0 time */
+ set_nbcfg_enable_bits(rs780_f0, 0xa0, 0x3F, 0x14);
+
+ /* Enables strict TM4 detection */
+ set_htiu_enable_bits(rs780_f0, 0x15, 0x1 << 22, 0x1 << 22);
+ /* Enables proprer DLL reset sequence */
+ set_htiu_enable_bits(rs780_f0, 0x16, 0x1 << 10, 0x1 << 10);
+
+ /* HyperTransport 3 Processor register settings to be done in northbridge */
+ /* Enables error-retry mode */
+ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0);
+ /* Enables scrambling */
+ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3);
+ /* Enables transmitter de-emphasis
+ * This depends on the PCB design and the trace */
+ /* TODO: */
+ /* Disables command throttling */
+ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
+ /* Sets Training 0 Time. See T0Time table for encodings */
+ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
+ /* TODO: */
+ #endif /* #if CONFIG_CAR_FAM10 == 1 */
+ }
+}
+
+#if CONFIG_CAR_FAM10 != 1 /* save some spaces */
+/*******************************************************
+* Optimize k8 with UMA.
+* See BKDG_NPT_0F guide for details.
+* The processor node is addressed by its Node ID on the HT link and can be
+* accessed with a device number in the PCI configuration space on Bus0.
+* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
+* to Device 25, and so on.
+* The processor implements configuration registers in PCI configuration
+* space using the following four headers
+* Function0: HT technology configuration
+* Function1: Address map configuration
+* Function2: DRAM and HT technology Trace mode configuration
+* Function3: Miscellaneous configuration
+*******************************************************/
+static void k8_optimization()
+{
+ device_t k8_f0, k8_f2, k8_f3;
+ msr_t msr;
+
+ printk_info("k8_optimization()\n");
+ k8_f0 = PCI_DEV(0, 0x18, 0);
+ k8_f2 = PCI_DEV(0, 0x18, 2);
+ k8_f3 = PCI_DEV(0, 0x18, 3);
+
+ /* 8.6.6 K8 Buffer Allocation Settings */
+ pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */
+ set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
+ set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 26, 3 << 26);
+ set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
+ /* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */
+
+ pci_write_config32(k8_f3, 0x70, 0x51220111);
+ pci_write_config32(k8_f3, 0x74, 0x50404021);
+ pci_write_config32(k8_f3, 0x78, 0x08002A00);
+ if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
+ pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */
+ else
+ pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */
+ set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
+
+ set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
+ set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
+ set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10);
+ set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
+ set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
+
+ msr = rdmsr(0xC001001F);
+ msr.lo &= ~(1 << 9);
+ msr.hi &= ~(1 << 4);
+ wrmsr(0xC001001F, msr);
+}
+#else
+#define k8_optimization() do{}while(0)
+#endif /* #if CONFIG_CAR_FAM10 != 1 */
+
+#if CONFIG_CAR_FAM10 == 1 /* save some spaces */
+void fam10_optimization()
+{
+ device_t cpu_f0, cpu_f2, cpu_f3;
+ msr_t msr;
+ u32 val;
+
+ printk_info("fam10_optimization()\n");
+
+ cpu_f0 = PCI_DEV(0, 0x18, 0);
+ cpu_f2 = PCI_DEV(0, 0x18, 2);
+ cpu_f3 = PCI_DEV(0, 0x18, 3);
+
+ /* 8.6.4.1 */
+ /* Table 8-13 */
+ pci_write_config32(cpu_f0, 0x90, 0x808502D0);
+ /* Table 8-14 */
+ pci_write_config32(cpu_f0, 0x94, 0x00000000);
+
+ /* Table 8-15 */
+ val = pci_read_config32(cpu_f0, 0x68);
+ val |= 1 << 24;
+ pci_write_config32(cpu_f0, 0x68, val);
+
+ /* Table 8-16 */
+ val = pci_read_config32(cpu_f0, 0x84);
+ val &= ~(1 << 12);
+ pci_write_config32(cpu_f0, 0x84, val);
+
+ /* Table 8-17 */
+ val = pci_read_config32(cpu_f2, 0x90);
+ val &= ~(1 << 10);
+ pci_write_config32(cpu_f2, 0x90, val);
+
+ /* Table 8-18 */
+ pci_write_config32(cpu_f3, 0x6C, 0x60018051);
+ /* Table 8-19 */
+ pci_write_config32(cpu_f3, 0x70, 0x60321151);
+ /* Table 8-20 */
+ pci_write_config32(cpu_f3, 0x74, 0x00980101);
+ /* Table 8-21 */
+ pci_write_config32(cpu_f3, 0x78, 0x00200C14);
+ /* Table 8-22 */
+ pci_write_config32(cpu_f3, 0x7C, 0x00070811); /* TODO: Check if L3 Cache is enabled. */
+
+ /* Table 8-23 */
+ Set_NB32(cpu_f3, 0x140, 0x00D33656);
+ /* Table 8-24 */
+ Set_NB32(cpu_f3, 0x144, 0x00000036);
+ /* Table 8-25 */
+ Set_NB32(cpu_f3, 0x148, 0x8000832A);
+ /* Table 8-26 */
+ Set_NB32(cpu_f3, 0x158, 0);
+ /* L3 Disabled: L3 Enabled: */
+ /* cores: 2 3 4 2 3 4 */
+ /* bit8:4 28 26 24 24 20 16 */
+ if (!l3Cache()) {
+ Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2);
+ } else {
+ Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (16 + 4*(4-cpu_core_number())) << 4 | 4);
+ }
+}
+#else
+#define fam10_optimization() do{}while(0)
+#endif /* #if CONFIG_CAR_FAM10 == 1 */
+
+/*****************************************
+* rs780_por_pcicfg_init()
+*****************************************/
+static void rs780_por_pcicfg_init(device_t nb_dev)
+{
+ /* enable PCI Memory Access */
+ set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
+ /* Set RCRB Enable */
+ set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1);
+ /* allow decode of 640k-1MB */
+ set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10);
+ /* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */
+ set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4);
+ /* Power Management Register Enable */
+ set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
+
+ /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+ * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
+ * BMMsgEn */
+ set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);
+
+ /* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
+ * Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */
+ set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05);
+ /* Reg94h[4:0] = 0x0 P drive strength offset 0
+ * Reg94h[6:5] = 0x2 P drive strength additive adjust */
+ set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40);
+
+ /* Reg94h[20:16] = 0x0 N drive strength offset 0
+ * Reg94h[22:21] = 0x2 N drive strength additive adjust */
+ set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40);
+
+ /* Reg80h[4:0] = 0x0 Termination offset
+ * Reg80h[6:5] = 0x2 Termination additive adjust */
+ set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40);
+
+ /* Reg80h[14] = 0x1 Enable receiver termination control */
+ set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40);
+
+ /* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
+ * Reg94h[14] = 0x1 Enable drive strength control */
+ set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4);
+
+ /* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
+ set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0);
+
+ /*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
+ * force this BAR as mem type in rs780_gfx.c */
+ set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
+}
+
+static void rs780_por_mc_index_init(device_t nb_dev)
+{
+ set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
+ set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
+ set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060);
+ set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000);
+ set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000);
+ set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E);
+ set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
+}
+
+static void rs780_por_misc_index_init(device_t nb_dev)
+{
+ /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
+ * Block non-snoop DMA request if PMArbDis is set.
+ * Set BMSetDis */
+ set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180);
+ set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040);
+
+ /* NBCFG (NBMISCIND 0x0): NB_CNTL -
+ * HIDE_NB_AGP_CAP ([0], default=1)HIDE
+ * HIDE_P2P_AGP_CAP ([1], default=1)HIDE
+ * HIDE_NB_GART_BAR ([2], default=1)HIDE
+ * AGPMODE30 ([4], default=0)DISABLE
+ * AGP30ENCHANCED ([5], default=0)DISABLE
+ * HIDE_AGP_CAP ([8], default=1)ENABLE */
+ set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
+
+ /* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
+ * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000);
+ * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */
+ set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
+
+ /* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */
+ set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500);
+
+ /* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */
+ set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000);
+
+ /* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */
+ set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008);
+
+ /*
+ * Enable access to DEV8
+ * Enable setPower message for all ports
+ */
+ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6);
+ set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20);
+ set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20);
+ set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20);
+ set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20);
+ set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20);
+ set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20);
+ set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20);
+ set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20, 1 << 20);
+ set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20, 1 << 20);
+
+ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
+ set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30);
+
+ set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x48);
+ /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
+ set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180);
+}
+
+/*****************************************
+* Some setting is from rpr. Some is from CIMx.
+*****************************************/
+static void rs780_por_htiu_index_init(device_t nb_dev)
+{
+#if 0 /* get from rpr. */
+ set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17);
+ set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0);
+ set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1);
+ set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9);
+ set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13);
+ set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17);
+ set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15);
+ set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25);
+ set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30);
+
+ set_htiu_enable_bits(nb_dev, 0x07, 0x1<<0, 0x1<<0);
+ set_htiu_enable_bits(nb_dev, 0x07, 0x1<<1, 0x0<<1);
+ set_htiu_enable_bits(nb_dev, 0x07, 0x1<<2, 0x0<<2);
+ set_htiu_enable_bits(nb_dev, 0x07, 0x1<<15, 0x1<<15);
+
+ set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<0, 0x1<<0);
+ set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<2, 0x2<<2);
+ set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<4, 0x0<<4);
+
+ /* A12 only */
+ set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<4, 0x1<<4);
+ set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<6, 0x1<<6);
+ set_htiu_enable_bits(nb_dev, 0x05, 0x1<<2, 0x1<<2);
+
+ set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF);
+#else /* get from CIM. It is more reliable than above. */
+ set_htiu_enable_bits(nb_dev, 0x05, (1<<10|1<<9), 1<<10 | 1<<9);
+ set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x04203A202);
+
+ set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x8001/* | 7 << 8 */); /* fam 10 */
+
+ set_htiu_enable_bits(nb_dev, 0x15, ~0xFFFFFFFF, 1<<31| 1<<30 | 1<<27);
+ set_htiu_enable_bits(nb_dev, 0x1C, ~0xFFFFFFFF, 0xFFFE0000);
+
+ set_htiu_enable_bits(nb_dev, 0x4B, (1<<11), 1<<11);
+
+ set_htiu_enable_bits(nb_dev, 0x0C, ~0xFFFFFFC0, 1<<0|1<<3);
+
+ set_htiu_enable_bits(nb_dev, 0x17, (1<<27|1<<1), 0x1<<1);
+ set_htiu_enable_bits(nb_dev, 0x17, 0x1 << 30, 0x1<<30);
+
+ set_htiu_enable_bits(nb_dev, 0x19, (0xFFFFF+(1<<31)), 0x186A0+(1<<31));
+
+ set_htiu_enable_bits(nb_dev, 0x16, (0x3F<<10), 0x7<<10);
+
+ set_htiu_enable_bits(nb_dev, 0x23, 0xFFFFFFF, 1<<28);
+
+ set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF);
+#endif
+}
+
+/*****************************************
+* Configure RS780 registers to power-on default RPR.
+* POR: Power On Reset
+* RPR: Register Programming Requirements
+*****************************************/
+static void rs780_por_init(device_t nb_dev)
+{
+ printk_info("rs780_por_init\n");
+ /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */
+ rs780_por_pcicfg_init(nb_dev);
+
+ /* ATINB_MCIND_POR_TABLE */
+ rs780_por_mc_index_init(nb_dev);
+
+ /* ATINB_MISCIND_POR_TABLE */
+ rs780_por_misc_index_init(nb_dev);
+
+ /* ATINB_HTIUNBIND_POR_TABLE */
+ rs780_por_htiu_index_init(nb_dev);
+
+ /* ATINB_CLKCFG_PORT_TABLE */
+ /* rs780 A11 SB Link full swing? */
+}
+
+/* enable CFG access to Dev8, which is the SB P2P Bridge */
+static void enable_rs780_dev8()
+{
+ set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
+}
+
+static void rs780_before_pci_init()
+{
+}
+
+static void rs780_early_setup()
+{
+ device_t nb_dev = PCI_DEV(0, 0, 0);
+ printk_info("rs780_early_setup()\n");
+
+ get_cpu_rev();
+
+ /* The printk_info(s) below cause the system unstable. */
+ switch (get_nb_rev(nb_dev)) {
+ case REV_RS780_A11:
+ /* printk_info("NB Revision is A11.\n"); */
+ break;
+ case REV_RS780_A12:
+ /* printk_info("NB Revision is A12.\n"); */
+ break;
+ case REV_RS780_A13:
+ /* printk_info("NB Revision is A13.\n"); */
+ break;
+ }
+
+ if (is_famly10())
+ fam10_optimization();
+ else
+ k8_optimization();
+
+ rs780_por_init(nb_dev);
+}
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c
new file mode 100644
index 0000000000..5e70b2d5d6
--- /dev/null
+++ b/src/southbridge/amd/rs780/rs780_gfx.c
@@ -0,0 +1,1194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * for rs780 internal graphics device
+ * device id of internal grphics:
+ * RS780: 0x9610
+ * RS780C: 0x9611
+ * RS780M: 0x9612
+ * RS780MC:0x9613
+ * RS780E: 0x9615
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include <cpu/x86/msr.h>
+#include "rs780.h"
+
+void set_pcie_reset();
+void set_pcie_dereset();
+
+#define CLK_CNTL_INDEX 0x8
+#define CLK_CNTL_DATA 0xC
+
+/* The Integrated Info Table. */
+ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;
+
+static u32 clkind_read(device_t dev, u32 index)
+{
+ u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+
+ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
+ return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
+}
+
+static void clkind_write(device_t dev, u32 index, u32 data)
+{
+ u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+ /* printk_info("gfx bar 2 %02x\n", gfx_bar2); */
+
+ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
+ *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data;
+}
+
+/*
+* pci_dev_read_resources thinks it is a IO type.
+* We have to force it to mem type.
+*/
+static void rs780_gfx_read_resources(device_t dev)
+{
+ printk_info("rs780_gfx_read_resources.\n");
+
+ /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
+ Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
+ which tells us it is a memory address base.
+ */
+ pci_write_config32(dev, 0x24, 0x00000000);
+
+ /* Get the normal pci resources of this device */
+ pci_dev_read_resources(dev);
+ compact_resources(dev);
+}
+
+typedef struct _MMIORANGE
+{
+ u32 Base;
+ u32 Limit;
+ u8 Attribute;
+} MMIORANGE;
+
+MMIORANGE MMIO[8], CreativeMMIO[8];
+
+MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
+{
+ int i;
+ for (i=0; i<8; i++)
+ {
+ if (pMMIO[i].Limit == 0)
+ return &pMMIO[i];
+ }
+ return 0;
+}
+void FreeMMIO(MMIORANGE* pMMIO)
+{
+ pMMIO->Base = 0;
+ pMMIO->Limit = 0;
+}
+
+#define CIM_STATUS u32
+#define CIM_SUCCESS 0x00000000
+#define CIM_ERROR 0x80000000
+#define CIM_UNSUPPORTED 0x80000001
+#define CIM_DISABLEPORT 0x80000002
+
+#define MMIO_ATTRIB_NP_ONLY 1
+#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
+#define MMIO_ATTRIB_SKIP_ZERO 1<<2
+
+u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
+{
+ int i;
+ MMIORANGE * TempRange;
+ for(i=0; i<8; i++)
+ {
+ if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
+ {
+ TempRange = AllocMMIO(pMMIO);
+ if(TempRange == 0) return 0x80000000;
+ TempRange->Base = Limit;
+ TempRange->Limit = pMMIO[i].Limit;
+ TempRange->Attribute = pMMIO[i].Attribute;
+ pMMIO[i].Limit = Base;
+ }
+ }
+ TempRange = AllocMMIO(pMMIO);
+ if(TempRange == 0) return 0x80000000;
+ TempRange->Base = Base;
+ TempRange->Limit = Limit;
+ TempRange->Attribute = Attribute;
+ return 0;
+}
+
+u8 FinalizeMMIO(MMIORANGE *pMMIO)
+{
+ int i, j, n = 0;
+ for(i=0; i<8; i++)
+ {
+ if (pMMIO[i].Base == pMMIO[i].Limit)
+ {
+ FreeMMIO(&pMMIO[i]);
+ continue;
+ }
+ for(j=0; j<i; j++)
+ {
+ if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
+ {
+ if (pMMIO[i].Base == pMMIO[j].Limit)
+ {
+ pMMIO[j].Limit = pMMIO[i].Limit;
+ FreeMMIO(&pMMIO[i]);
+ }
+ if (pMMIO[i].Limit == pMMIO[j].Base)
+ {
+ pMMIO[j].Base = pMMIO[i].Base;
+ FreeMMIO(&pMMIO[i]);
+ }
+ }
+ }
+ }
+ for (i=0; i<8; i++)
+ {
+ if (pMMIO[i].Limit != 0) n++;
+ }
+ return n;
+}
+
+CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
+{
+ CIM_STATUS Status = CIM_UNSUPPORTED;
+ u8 Bus, Dev, Reg, BusStart, BusEnd;
+ u32 Value;
+ device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ device_t tempdev;
+ Value = pci_read_config32(dev0x14, 0x18);
+ BusStart = (Value >> 8) & 0xFF;
+ BusEnd = (Value >> 16) & 0xFF;
+ for(Bus = BusStart; Bus <= BusEnd; Bus++)
+ {
+ for(Dev = 0; Dev <= 0x1f; Dev++)
+ {
+ tempdev = dev_find_slot(Bus, Dev << 3);
+ Value = pci_read_config32(tempdev, 0);
+ printk_debug("Dev ID %x \n", Value);
+ if((Value & 0xffff) == 0x1102)
+ {//Creative
+ //Found Creative SB
+ u32 MMIOStart = 0xffffffff;
+ u32 MMIOLimit = 0;
+ for(Reg = 0x10; Reg < 0x20; Reg+=4)
+ {
+ u32 BaseA, LimitA;
+ BaseA = pci_read_config32(tempdev, Reg);
+ Value = BaseA;
+ if(!(Value & 0x01))
+ {
+ Value = Value & 0xffffff00;
+ if(Value != 0)
+ {
+ if(MMIOStart > Value)
+ MMIOStart = Value;
+ LimitA = 0xffffffff;
+ //WritePCI(PciAddress,AccWidthUint32,&LimitA);
+ pci_write_config32(tempdev, Reg, LimitA);
+ //ReadPCI(PciAddress,AccWidthUint32,&LimitA);
+ LimitA = pci_read_config32(tempdev, Reg);
+ LimitA = Value + (~LimitA + 1);
+ //WritePCI(PciAddress,AccWidthUint32,&BaseA);
+ pci_write_config32(tempdev, Reg, BaseA);
+ if (LimitA > MMIOLimit)
+ MMIOLimit = LimitA;
+ }
+ }
+ }
+ printk_debug(" MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
+ if (MMIOStart < MMIOLimit)
+ {
+ Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
+ if(Status == CIM_ERROR) return Status;
+ }
+ }
+ }
+ }
+ if(Status == CIM_SUCCESS)
+ {
+ //Lets optimize MMIO
+ if(FinalizeMMIO(pMMIO) > 4)
+ {
+ Status = CIM_ERROR;
+ }
+ }
+
+ return Status;
+}
+
+void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
+{
+ int i, j, n = 7;
+ device_t k8_f1;
+ u32 temp32;
+
+ k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+
+ for(i = 0; i < 8; i++)
+ {
+ int k = 0, MmioReg;
+ u32 Base = 0;
+ u32 Limit = 0;
+ for(j = 0; j < 8; j++)
+ {
+ if (Base < pMMIO[j].Base)
+ {
+ Base = pMMIO[j].Base;
+ k = j;
+ }
+ }
+ if(pMMIO[k].Limit != 0)
+ {
+ if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
+ {
+ Base = 0;
+ }
+ else
+ {
+ Base = pMMIO[k].Base | 0x3;
+ Limit= ((pMMIO[k].Limit - 1) & 0xffffff00) | pMMIO[k].Attribute | (LinkID << 4);
+ }
+ FreeMMIO(&pMMIO[k]);
+ }
+ if (Attribute & MMIO_ATTRIB_SKIP_ZERO && Base == 0 && Limit == 0) continue;
+ MmioReg = (Attribute & MMIO_ATTRIB_BOTTOM_TO_TOP)?n:(7-n);
+ n--;
+ //RWPCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,0x0,0x0);
+ pci_write_config32(k8_f1, 0x80+MmioReg*8, 0);
+
+ //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x84+MmioReg*8),AccWidthUint32 |S3_SAVE,&Limit);
+ pci_write_config32(k8_f1, 0x84+MmioReg*8, Limit);
+
+ //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,&Base);
+ pci_write_config32(k8_f1, 0x80+MmioReg*8, Base);
+ }
+}
+
+static void internal_gfx_pci_dev_init(struct device *dev)
+{
+ unsigned char * bpointer;
+ volatile u32 * GpuF0MMReg;
+ volatile u32 * pointer;
+ int i;
+ u16 command;
+ u32 value, temp, Base32, Limit32;
+ CIM_STATUS Status;
+ u16 deviceid, vendorid;
+ device_t nb_dev = dev_find_slot(0, 0);
+ device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+ device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)dev->chip_info;
+
+ deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
+ vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
+ printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+ deviceid, vendorid);
+
+ command = pci_read_config16(dev, 0x04);
+ command |= 0x7;
+ pci_write_config16(dev, 0x04, command);
+
+ /* Clear vgainfo. */
+ bpointer = (unsigned char *) &vgainfo;
+ for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
+ {
+ *bpointer = 0;
+ bpointer++;
+ }
+
+ GpuF0MMReg = (u32 *)pci_read_config32(dev, 0x18);
+
+ /* GFX_InitFBAccess. */
+ value = nbmc_read_index(nb_dev, 0x10);
+ *(GpuF0MMReg + 0x2000/4) = 0x11;
+ *(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
+ *(GpuF0MMReg + 0x2c04/4) = ((value&0xff0)<<8);
+ *(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
+ *(GpuF0MMReg + 0x2000/4) = 0x00000011;
+ *(GpuF0MMReg + 0x200c/4) = 0x00000020;
+ *(GpuF0MMReg + 0x2010/4) = 0x10204810;
+ *(GpuF0MMReg + 0x2010/4) = 0x00204810;
+ *(GpuF0MMReg + 0x2014/4) = 0x10408810;
+ *(GpuF0MMReg + 0x2014/4) = 0x00408810;
+ *(GpuF0MMReg + 0x2414/4) = 0x00000080;
+ *(GpuF0MMReg + 0x2418/4) = 0x84422415;
+ *(GpuF0MMReg + 0x2418/4) = 0x04422415;
+ *(GpuF0MMReg + 0x5490/4) = 0x00000001;
+ *(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
+ /* Force allow LDT_STOP Cool'n'Quiet workaround. */
+ *(GpuF0MMReg + 0x655c/4) |= 1<<4;
+ /* GFX_InitFBAccess finished. */
+
+ /* GFX_StartMC. */
+#if (CONFIG_GFXUMA == 1) /* for UMA mode. */
+ /* MC_INIT_COMPLETE. */
+ set_nbmc_enable_bits(nb_dev, 0x2, 0, 1<<31);
+ /* MC_STARTUP, MC_POWERED_UP and MC_VMODE.*/
+ set_nbmc_enable_bits(nb_dev, 0x1, 1<<18, 1|1<<2);
+
+ set_nbmc_enable_bits(nb_dev, 0xb1, 0, 1<<6);
+ set_nbmc_enable_bits(nb_dev, 0xc3, 0, 1);
+ nbmc_write_index(nb_dev, 0x07, 0x18);
+ nbmc_write_index(nb_dev, 0x06, 0x00000102);
+ nbmc_write_index(nb_dev, 0x09, 0x40000008);
+ set_nbmc_enable_bits(nb_dev, 0x6, 0, 1<<31);
+ /* GFX_StartMC finished. */
+#else
+ /* for SP mode. */
+ set_nbmc_enable_bits(nb_dev, 0xaa, 0xf0, 0x30);
+ set_nbmc_enable_bits(nb_dev, 0xce, 0xf0, 0x30);
+ set_nbmc_enable_bits(nb_dev, 0xca, 0xff000000, 0x47000000);
+ set_nbmc_enable_bits(nb_dev, 0xcb, 0x3f000000, 0x01000000);
+ set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<0);
+ set_nbmc_enable_bits(nb_dev, 0x04, 0, 1<<31);
+ set_nbmc_enable_bits(nb_dev, 0xb4, 0x3f, 0x3f);
+ set_nbmc_enable_bits(nb_dev, 0xb4, 0, 1<<6);
+ set_nbmc_enable_bits(nb_dev, 0xc3, 1<<11, 0);
+ set_nbmc_enable_bits(nb_dev, 0xa0, 1<<29, 0);
+ nbmc_write_index(nb_dev, 0xa4, 0x3484576f);
+ nbmc_write_index(nb_dev, 0xa5, 0x222222df);
+ nbmc_write_index(nb_dev, 0xa6, 0x00000000);
+ nbmc_write_index(nb_dev, 0xa7, 0x00000000);
+ set_nbmc_enable_bits(nb_dev, 0xc3, 1<<8, 0);
+ udelay(10);
+ set_nbmc_enable_bits(nb_dev, 0xc3, 1<<9, 0);
+ udelay(10);
+ set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<2);
+ udelay(200);
+ set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<3);
+ set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<31);
+ udelay(500);
+ set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<31);
+ set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<30);
+ set_nbmc_enable_bits(nb_dev, 0xa0, 1<<31, 0);
+ set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<29);
+ nbmc_write_index(nb_dev, 0xa4, 0x23484576);
+ nbmc_write_index(nb_dev, 0xa5, 0x00000000);
+ nbmc_write_index(nb_dev, 0xa6, 0x00000000);
+ nbmc_write_index(nb_dev, 0xa7, 0x00000000);
+ /* GFX_StartMC finished. */
+
+ /* GFX_SPPowerManagment, don't care for new. */
+ /* Post MC Init table programming. */
+ set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b);
+
+ /* Do we need Write and Read Calibration? */
+ /* GFX_Init finished. */
+#endif
+
+ /* GFX_InitIntegratedInfo. */
+ /* fill the Integrated Info Table. */
+ vgainfo.sHeader.usStructureSize = sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2);
+ vgainfo.sHeader.ucTableFormatRevision = 1;
+ vgainfo.sHeader.ucTableContentRevision = 2;
+
+#if (CONFIG_GFXUMA == 0) /* SP mode. */
+ vgainfo.ulBootUpSidePortClock = 667*100;
+ vgainfo.ucMemoryType = 3;
+ vgainfo.ulMinSidePortClock = 333*100;
+#endif
+
+ vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */
+ vgainfo.ulReserved1[0] = 0; vgainfo.ulReserved1[1] = 0;
+ value = pci_read_config32(k8_f2, 0x94);
+ printk_debug("MEMCLK = %x\n", value&0x7);
+ vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */
+ vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */
+ vgainfo.ulMinSidePortClock = 0; /* disable SP. */
+ for(i=0; i<6; i++)
+ vgainfo.ulReserved2[i] = 0;
+ vgainfo.ulSystemConfig = 0;
+ //vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1;
+ vgainfo.ulBootUpReqDisplayVector = 0; //?
+ vgainfo.ulOtherDisplayMisc = 0; //?
+ vgainfo.ulDDISlot1Config = 0x000c0011; //0; //?
+ vgainfo.ulDDISlot2Config = 0x00130022; //0; //?
+ vgainfo.ucMemoryType = 2;
+ /* UMA Channel Number: 1 or 2. */
+ vgainfo.ucUMAChannelNumber = 2;
+ vgainfo.ucDockingPinBit = 0; //?
+ vgainfo.ucDockingPinPolarity = 0; //?
+ vgainfo.ulDockingPinCFGInfo = 0; //?
+ vgainfo.ulCPUCapInfo = 3; /* K8. */
+
+ /* page 5-19 on BDG. */
+ vgainfo.usNumberOfCyclesInPeriod = 0x8019;
+ vgainfo.usMaxNBVoltage = 0x1a;
+ vgainfo.usMinNBVoltage = 0;
+ vgainfo.usBootUpNBVoltage = 0x1a;
+
+ value = pci_read_config32(nb_dev, 0xd0);
+ printk_debug("NB HT speed = %x.\n", value);
+ value = pci_read_config32(k8_f0, 0x88);
+ printk_debug("CPU HT speed = %x.\n", value);
+ vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */
+
+ /* HT width. */
+ value = pci_read_config32(nb_dev, 0xc8);
+ printk_debug("HT width = %x.\n", value);
+ vgainfo.usMinHTLinkWidth = 16;
+ vgainfo.usMaxHTLinkWidth = 16;
+ vgainfo.usUMASyncStartDelay = 322;
+ vgainfo.usUMADataReturnTime = 86;
+ vgainfo.usLinkStatusZeroTime = 0x00c8; //0; //?
+ vgainfo.usReserved = 0;
+ vgainfo.ulHighVoltageHTLinkFreq = 100 * 100;
+ vgainfo.ulLowVoltageHTLinkFreq = 100 * 100;
+ vgainfo.usMaxUpStreamHTLinkWidth = 16;
+ vgainfo.usMaxDownStreamHTLinkWidth = 16;
+ vgainfo.usMinUpStreamHTLinkWidth = 16;
+ vgainfo.usMinDownStreamHTLinkWidth = 16;
+ for(i=0; i<97; i++)
+ vgainfo.ulReserved3[i] = 0;
+
+ /* Transfer the Table to VBIOS. */
+ pointer = (u32 *)&vgainfo;
+ for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
+ {
+#if (CONFIG_GFXUMA == 1)
+ *GpuF0MMReg = 0x80000000 + 0x10000000 - 512 + i;
+#else
+ *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
+#endif
+ *(GpuF0MMReg+1) = *pointer++;
+ }
+
+ /* GFX_InitLate. */
+ {
+ u8 temp8;
+ temp8 = pci_read_config8(dev, 0x4);
+ //temp8 &= ~1; /* CIM clears this bit. Strangely, I can'd. */
+ temp8 |= 1<<1|1<<2;
+ pci_write_config8(dev, 0x4, temp8);
+ }
+
+#if 0 /* Trust the original resource allocation. Don't do it again. */
+ /* NB_SetupMGMMIO. */
+
+ /* clear MMIO and CreativeMMIO. */
+ bpointer = (unsigned char *)MMIO;
+ for(i=0; i<sizeof(MMIO); i++)
+ {
+ *bpointer = 0;
+ bpointer++;
+ }
+ bpointer = (unsigned char *)CreativeMMIO;
+ for(i=0; i<sizeof(CreativeMMIO); i++)
+ {
+ *bpointer = 0;
+ bpointer++;
+ }
+
+ /* Set MMIO ranges in K8. */
+ /* Set MMIO TOM - 4G. */
+ SetMMIO(0x400<<12, 0x1000000, 0x80, &MMIO[0]);
+ /* Set MMIO for VGA Legacy FB. */
+ SetMMIO(0xa00, 0xc00, 0x80, &MMIO[0]);
+
+ /* Set MMIO for non prefetchable P2P. */
+ temp = pci_read_config32(dev0x14, 0x20);
+ Base32 = (temp & 0x0fff0) << 8;
+ Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
+ if(Base32 < Limit32)
+ {
+ Status = GetCreativeMMIO(&CreativeMMIO[0]);
+ if(Status != CIM_ERROR)
+ SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
+ }
+ /* Set MMIO for prefetchable P2P. */
+ if(Status != CIM_ERROR)
+ {
+ temp = pci_read_config32(dev0x14, 0x24);
+
+ Base32 = (temp & 0x0fff0) <<8;
+ Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
+ if(Base32 < Limit32)
+ SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
+ }
+
+ FinalizeMMIO(&MMIO[0]);
+
+ ProgramMMIO(&CreativeMMIO[0], 0, MMIO_ATTRIB_NP_ONLY);
+ ProgramMMIO(&MMIO[0], 0, MMIO_ATTRIB_NP_ONLY | MMIO_ATTRIB_BOTTOM_TO_TOP | MMIO_ATTRIB_SKIP_ZERO);
+#endif
+
+ pci_dev_init(dev);
+
+ /* clk ind */
+ clkind_write(dev, 0x08, 0x01);
+ clkind_write(dev, 0x0C, 0x22);
+ clkind_write(dev, 0x0F, 0x0);
+ clkind_write(dev, 0x11, 0x0);
+ clkind_write(dev, 0x12, 0x0);
+ clkind_write(dev, 0x14, 0x0);
+ clkind_write(dev, 0x15, 0x0);
+ clkind_write(dev, 0x16, 0x0);
+ clkind_write(dev, 0x17, 0x0);
+ clkind_write(dev, 0x18, 0x0);
+ clkind_write(dev, 0x19, 0x0);
+ clkind_write(dev, 0x1A, 0x0);
+ clkind_write(dev, 0x1B, 0x0);
+ clkind_write(dev, 0x1C, 0x0);
+ clkind_write(dev, 0x1D, 0x0);
+ clkind_write(dev, 0x1E, 0x0);
+ clkind_write(dev, 0x26, 0x0);
+ clkind_write(dev, 0x27, 0x0);
+ clkind_write(dev, 0x28, 0x0);
+ clkind_write(dev, 0x5C, 0x0);
+}
+
+
+/*
+* Set registers in RS780 and CPU to enable the internal GFX.
+* Please refer to CIM source code and BKDG.
+*/
+extern uint64_t uma_memory_base, uma_memory_size;
+
+static void rs780_internal_gfx_enable(device_t dev)
+{
+ u32 l_dword;
+ int i;
+ device_t k8_f0 = 0, k8_f2 = 0;
+ device_t nb_dev = dev_find_slot(0, 0);
+ msr_t sysmem;
+
+#if (CONFIG_GFXUMA == 0)
+ u32 FB_Start, FB_End;
+#endif
+
+ printk_info("rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
+
+ sysmem = rdmsr(0xc001001a);
+ printk_info("sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
+
+ /* The system top memory in 780. */
+ pci_write_config32(nb_dev, 0x90, sysmem.lo);
+ htiu_write_index(nb_dev, 0x30, 0);
+ htiu_write_index(nb_dev, 0x31, 0);
+
+ /* Disable external GFX and enable internal GFX. */
+ l_dword = pci_read_config32(nb_dev, 0x8c);
+ l_dword &= ~(1<<0);
+ l_dword |= 1<<1;
+ pci_write_config32(nb_dev, 0x8c, l_dword);
+
+ /* NB_SetDefaultIndexes */
+ pci_write_config32(nb_dev, 0x94, 0x7f);
+ pci_write_config32(nb_dev, 0x60, 0x7f);
+ pci_write_config32(nb_dev, 0xe0, 0);
+
+ /* NB_InitEarlyNB finished. */
+
+ /* LPC DMA Deadlock workaround? */
+ /* GFX_InitCommon*/
+ k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ l_dword = pci_read_config32(k8_f0, 0x68);
+ l_dword &= ~(3 << 21);
+ l_dword |= (1 << 21);
+ pci_write_config32(k8_f0, 0x68, l_dword);
+
+ /* GFX_InitCommon. */
+ nbmc_write_index(nb_dev, 0x23, 0x00c00010);
+ set_nbmc_enable_bits(nb_dev, 0x16, 1<<15, 1<<15);
+ set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
+ set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
+
+#if (CONFIG_GFXUMA == 1)
+ /* GFX_InitUMA. */
+ /* Copy CPU DDR Controller to NB MC. */
+ k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ for (i = 0; i < 12; i++)
+ {
+ l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
+ nbmc_write_index(nb_dev, 0x30 + i, l_dword);
+ }
+
+ l_dword = pci_read_config32(k8_f2, 0x80);
+ nbmc_write_index(nb_dev, 0x3c, l_dword);
+
+ l_dword = pci_read_config32(k8_f2, 0x94);
+ if(l_dword & (1<<22))
+ set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<16);
+ else
+ set_nbmc_enable_bits(nb_dev, 0x3c, 1<<16, 0);
+
+ if(l_dword & (1<<8))
+ set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<17);
+ else
+ set_nbmc_enable_bits(nb_dev, 0x3c, 1<<17, 0);
+
+ l_dword = pci_read_config32(k8_f2, 0x90);
+ if(l_dword & (1<<10))
+ set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<18);
+ else
+ set_nbmc_enable_bits(nb_dev, 0x3c, 1<<18, 0);
+
+ /* Set UMA in the 780 side. */
+ /* UMA start address, size. */
+ /* The same value in spite of system memory size. */
+ nbmc_write_index(nb_dev, 0x10, 0xcfffc000);
+ nbmc_write_index(nb_dev, 0x11, uma_memory_base);
+ nbmc_write_index(nb_dev, 0x12, 0);
+ nbmc_write_index(nb_dev, 0xf0, 256);
+ /* GFX_InitUMA finished. */
+#else
+ /* GFX_InitSP. */
+ /* SP memory:Hynix HY5TQ1G631ZNFP. 128MB = 64M * 16. 667MHz. DDR3. */
+
+ /* Enable Async mode. */
+ set_nbmc_enable_bits(nb_dev, 0x06, 7<<8, 1<<8);
+ set_nbmc_enable_bits(nb_dev, 0x08, 1<<10, 0);
+ /* The last item in AsynchMclkTaskFileIndex. Why? */
+ /* MC_MPLL_CONTROL2. */
+ nbmc_write_index(nb_dev, 0x07, 0x40100028);
+ /* MC_MPLL_DIV_CONTROL. */
+ nbmc_write_index(nb_dev, 0x0b, 0x00000028);
+ /* MC_MPLL_FREQ_CONTROL. */
+ set_nbmc_enable_bits(nb_dev, 0x09, 3<<12|15<<16|15<<8, 1<<12|4<<16|0<<8);
+ /* MC_MPLL_CONTROL3. For PM. */
+ set_nbmc_enable_bits(nb_dev, 0x08, 0xff<<13, 1<<13|1<<18);
+ /* MPLL_CAL_TRIGGER. */
+ set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<0);
+ udelay(200); /* time is long enough? */
+ set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<1);
+ set_nbmc_enable_bits(nb_dev, 0x06, 1<<0, 0);
+ /* MCLK_SRC_USE_MPLL. */
+ set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<20);
+
+ /* Pre Init MC. */
+ nbmc_write_index(nb_dev, 0x01, 0x88108280);
+ set_nbmc_enable_bits(nb_dev, 0x02, ~(1<<20), 0x00030200);
+ nbmc_write_index(nb_dev, 0x04, 0x08881018);
+ nbmc_write_index(nb_dev, 0x05, 0x000000bb);
+ nbmc_write_index(nb_dev, 0x0c, 0x0f00001f);
+ nbmc_write_index(nb_dev, 0xa1, 0x01f10000);
+ /* MCA_INIT_DLL_PM. */
+ set_nbmc_enable_bits(nb_dev, 0xc9, 1<<24, 1<<24);
+ nbmc_write_index(nb_dev, 0xa2, 0x74f20000);
+ nbmc_write_index(nb_dev, 0xa3, 0x8af30000);
+ nbmc_write_index(nb_dev, 0xaf, 0x47d0a41c);
+ nbmc_write_index(nb_dev, 0xb0, 0x88800130);
+ nbmc_write_index(nb_dev, 0xb1, 0x00000040);
+ nbmc_write_index(nb_dev, 0xb4, 0x41247000);
+ nbmc_write_index(nb_dev, 0xb5, 0x00066664);
+ nbmc_write_index(nb_dev, 0xb6, 0x00000022);
+ nbmc_write_index(nb_dev, 0xb7, 0x00000044);
+ nbmc_write_index(nb_dev, 0xb8, 0xbbbbbbbb);
+ nbmc_write_index(nb_dev, 0xb9, 0xbbbbbbbb);
+ nbmc_write_index(nb_dev, 0xba, 0x55555555);
+ nbmc_write_index(nb_dev, 0xc1, 0x00000000);
+ nbmc_write_index(nb_dev, 0xc2, 0x00000000);
+ nbmc_write_index(nb_dev, 0xc3, 0x80006b00);
+ nbmc_write_index(nb_dev, 0xc4, 0x00066664);
+ nbmc_write_index(nb_dev, 0xc5, 0x00000000);
+ nbmc_write_index(nb_dev, 0xd2, 0x00000022);
+ nbmc_write_index(nb_dev, 0xd3, 0x00000044);
+ nbmc_write_index(nb_dev, 0xd6, 0x00050005);
+ nbmc_write_index(nb_dev, 0xd7, 0x00000000);
+ nbmc_write_index(nb_dev, 0xd8, 0x00700070);
+ nbmc_write_index(nb_dev, 0xd9, 0x00700070);
+ nbmc_write_index(nb_dev, 0xe0, 0x00200020);
+ nbmc_write_index(nb_dev, 0xe1, 0x00200020);
+ nbmc_write_index(nb_dev, 0xe8, 0x00200020);
+ nbmc_write_index(nb_dev, 0xe9, 0x00200020);
+ nbmc_write_index(nb_dev, 0xe0, 0x00180018);
+ nbmc_write_index(nb_dev, 0xe1, 0x00180018);
+ nbmc_write_index(nb_dev, 0xe8, 0x00180018);
+ nbmc_write_index(nb_dev, 0xe9, 0x00180018);
+
+ /* Misc options. */
+ /* Memory Termination. */
+ set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044);
+ set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00);
+#if 0
+ /* Controller Termation. */
+ set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000);
+#endif
+
+ /* OEM Init MC. 667MHz. */
+ nbmc_write_index(nb_dev, 0xa8, 0x7a5aaa78);
+ nbmc_write_index(nb_dev, 0xa9, 0x514a2319);
+ nbmc_write_index(nb_dev, 0xaa, 0x54400520);
+ nbmc_write_index(nb_dev, 0xab, 0x441460ff);
+ nbmc_write_index(nb_dev, 0xa0, 0x20f00a48);
+ set_nbmc_enable_bits(nb_dev, 0xa2, ~(0xffffffc7), 0x10);
+ nbmc_write_index(nb_dev, 0xb2, 0x00000303);
+ set_nbmc_enable_bits(nb_dev, 0xb1, ~(0xffffff70), 0x45);
+ /* Do it later. */
+ /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
+
+ /* Init PM timing. */
+ for(i=0; i<4; i++)
+ {
+ l_dword = nbmc_read_index(nb_dev, 0xa0+i);
+ nbmc_write_index(nb_dev, 0xc8+i, l_dword);
+ }
+ for(i=0; i<4; i++)
+ {
+ l_dword = nbmc_read_index(nb_dev, 0xa8+i);
+ nbmc_write_index(nb_dev, 0xcc+i, l_dword);
+ }
+ l_dword = nbmc_read_index(nb_dev, 0xb1);
+ set_nbmc_enable_bits(nb_dev, 0xc8, 0xff<<24, ((l_dword&0x0f)<<24)|((l_dword&0xf00)<<20));
+
+ /* Init MC FB. */
+ /* FB_Start = ; FB_End = ; iSpSize = 0x0080, 128MB. */
+ nbmc_write_index(nb_dev, 0x11, 0x40000000);
+ FB_Start = 0xc00 + 0x080;
+ FB_End = 0xc00 + 0x080;
+ nbmc_write_index(nb_dev, 0x10, (((FB_End&0xfff)<<20)-0x10000)|(((FB_Start&0xfff)-0x080)<<4));
+ set_nbmc_enable_bits(nb_dev, 0x0d, ~0x000ffff0, (FB_Start&0xfff)<<20);
+ nbmc_write_index(nb_dev, 0x0f, 0);
+ nbmc_write_index(nb_dev, 0x0e, (FB_Start&0xfff)|(0xaaaa<<12));
+#endif
+
+ /* GFX_InitSP finished. */
+}
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations pcie_ops = {
+ .read_resources = rs780_gfx_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs780_gfx_init, */
+ .scan_bus = 0,
+ .enable = rs780_internal_gfx_enable,
+ .ops_pci = &lops_pci,
+};
+
+/*
+ * We should list all of them here.
+ * */
+static struct pci_driver pcie_driver_780 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX,
+};
+
+static struct pci_driver pcie_driver_780c __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX,
+};
+static struct pci_driver pcie_driver_780m __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX,
+};
+static struct pci_driver pcie_driver_780mc __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX,
+};
+static struct pci_driver pcie_driver_780e __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX,
+};
+
+/* step 12 ~ step 14 from rpr */
+static void single_port_configuration(device_t nb_dev, device_t dev)
+{
+ u8 result, width;
+ u32 reg32;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+ printk_info("rs780_gfx_init single_port_configuration.\n");
+
+ /* step 12 training, releases hold training for GFX port 0 (device 2) */
+ PcieReleasePortTraining(nb_dev, dev, 2);
+ result = PcieTrainPort(nb_dev, dev, 2);
+ printk_info("rs780_gfx_init single_port_configuration step12.\n");
+
+ /* step 13 Power Down Control */
+ /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
+ set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+
+ /* step 13.a Link Training was NOT successful */
+ if (!result) {
+ set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
+ set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
+ if (cfg->gfx_tmds)
+ nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
+ else {
+ nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
+ }
+ } else { /* step 13.b Link Training was successful */
+ set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
+ reg32 = nbpcie_p_read_index(dev, 0x29);
+ width = reg32 & 0xFF;
+ printk_debug("GFX Inactive Lanes = 0x%x.\n", width);
+ switch (width) {
+ case 1:
+ case 2:
+ nbpcie_ind_write_index(nb_dev, 0x65,
+ cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
+ break;
+ case 4:
+ nbpcie_ind_write_index(nb_dev, 0x65,
+ cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
+ break;
+ case 8:
+ nbpcie_ind_write_index(nb_dev, 0x65,
+ cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
+ break;
+ }
+ }
+ printk_info("rs780_gfx_init single_port_configuration step13.\n");
+
+ /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
+ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
+ printk_info("rs780_gfx_init single_port_configuration step14.\n");
+}
+
+static void dual_port_configuration(device_t nb_dev, device_t dev)
+{
+ u8 result, width;
+ u32 reg32, dev_ind = dev->path.pci.devfn >> 3;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+ /* 5.4.1.2 Dual Port Configuration */
+ set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+ set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
+ set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+
+ /* 5.7. Training for Device 2 */
+ /* 5.7.1. Releases hold training for GFX port 0 (device 2) */
+ PcieReleasePortTraining(nb_dev, dev, dev_ind);
+ /* 5.7.2- 5.7.9. PCIE Link Training Sequence */
+ result = PcieTrainPort(nb_dev, dev, dev_ind);
+
+ /* Power Down Control for Device 2 */
+ /* Link Training was NOT successful */
+ if (!result) {
+ /* Powers down all lanes for port A */
+ /* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */
+ /* Note: I have to disable the slot where there isnt a device,
+ * otherwise the system will hang. I dont know why. */
+ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
+
+ } else { /* step 16.b Link Training was successful */
+ reg32 = nbpcie_p_read_index(dev, 0xa2);
+ width = (reg32 >> 4) & 0x7;
+ printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+ switch (width) {
+ case 1:
+ case 2:
+ nbpcie_ind_write_index(nb_dev, 0x65,
+ cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
+ break;
+ case 4:
+ nbpcie_ind_write_index(nb_dev, 0x65,
+ cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
+ break;
+ }
+ }
+}
+
+/* For single port GFX configuration Only
+* width:
+* 000 = x16
+* 001 = x1
+* 010 = x2
+* 011 = x4
+* 100 = x8
+* 101 = x12 (not supported)
+* 110 = x16
+*/
+static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
+{
+ u32 reg32;
+ device_t sb_dev;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+ /* step 5.9.1.1 */
+ reg32 = nbpcie_p_read_index(dev, 0xa2);
+
+ /* step 5.9.1.2 */
+ set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+ /* step 5.9.1.3 */
+ set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
+ /* step 5.9.1.4 */
+ set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
+ /* step 5.9.2.4 */
+ if (0 == cfg->gfx_reconfiguration)
+ set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
+
+ /* step 5.9.1.5 */
+ do {
+ reg32 = nbpcie_p_read_index(dev, 0xa2);
+ }
+ while (reg32 & 0x100);
+
+ /* step 5.9.1.6 */
+ sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+ do {
+ reg32 = pci_ext_read_config32(nb_dev, sb_dev,
+ PCIE_VC0_RESOURCE_STATUS);
+ } while (reg32 & VC_NEGOTIATION_PENDING);
+
+ /* step 5.9.1.7 */
+ reg32 = nbpcie_p_read_index(dev, 0xa2);
+ if (((reg32 & 0x70) >> 4) != 0x6) {
+ /* the unused lanes should be powered off. */
+ }
+
+ /* step 5.9.1.8 */
+ set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
+}
+
+/*
+* GFX Core initialization, dev2, dev3
+*/
+void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
+{
+ u16 reg16;
+ u32 reg32;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+ printk_info("rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+ nb_dev, dev, port);
+
+ /* GFX Core Initialization */
+ //if (port == 2) return;
+
+ /* step 1, lane reversal (only need if CMOS option is enabled) */
+ if (cfg->gfx_lane_reversal) {
+ set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+ if (cfg->gfx_dual_slot)
+ set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+ }
+ printk_info("rs780_gfx_init step1.\n");
+
+ /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+ /* AMD calls the configuration CrossFire */
+ if (cfg->gfx_dual_slot)
+ set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+ printk_info("rs780_gfx_init step2.\n");
+
+ /* step 2, TMDS, (only need if CMOS option is enabled) */
+ if (cfg->gfx_tmds) {
+ }
+
+#if 1 /* external clock mode */
+ /* table 5-22, 5.9.1. REFCLK */
+ /* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
+ * REFCLK PAD can be driven by an external source. */
+ /* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
+ set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 0 << 29 | 1 << 28);
+
+ /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
+ /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
+ /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
+ set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
+ 1 << 6 | 1 << 8 | 1 << 10);
+ reg32 = nbmisc_read_index(nb_dev, 0x28);
+ printk_info("misc 28 = %x\n", reg32);
+
+ /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
+ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
+#else /* internal clock mode */
+ /* table 5-23, 5.9.1. REFCLK */
+ /* 5.9.1.1. Enables the GFX REFCLK transmitter so that the GFX
+ * REFCLK PAD can be driven by the SB REFCLK. */
+ /* 5.9.1.2. Disables GFX REFCLK receiver from receiving the
+ * REFCLK from an external source.*/
+ set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 1 << 29 | 0 << 28);
+
+ /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
+ /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
+ /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
+ set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
+ 0);
+ reg32 = nbmisc_read_index(nb_dev, 0x28);
+ printk_info("misc 28 = %x\n", reg32);
+
+ /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
+ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
+#endif
+
+ /* step 5.9.3, GFX overclocking, (only need if CMOS option is enabled) */
+ /* 5.9.3.1. Increases PLL BW for 6G operation.*/
+ /* set_nbmisc_enable_bits(nb_dev, 0x36, 0x3FF << 4, 0xB5 << 4); */
+ /* skip */
+
+ /* step 5.9.4, reset the GFX link */
+ /* step 5.9.4.1 asserts both calibration reset and global reset */
+ set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
+
+ /* step 5.9.4.2 de-asserts calibration reset */
+ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
+
+ /* step 5.9.4.3 wait for at least 200us */
+ udelay(300);
+
+ /* step 5.9.4.4 de-asserts global reset */
+ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
+
+ /* 5.9.5 Reset PCIE_GFX Slot */
+ /* It is done in mainboard.c */
+ set_pcie_reset();
+ mdelay(1);
+ set_pcie_dereset();
+
+ /* step 5.9.8 program PCIE memory mapped configuration space */
+ /* done by enable_pci_bar3() before */
+
+ /* step 7 compliance state, (only need if CMOS option is enabled) */
+ /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
+ if (cfg->gfx_compliance) {
+ /* force compliance */
+ set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
+ /* release hold training for device 2. GFX initialization is done. */
+ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
+ dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
+ printk_info("rs780_gfx_init step7.\n");
+ return;
+ }
+
+ /* 5.9.12 Core Initialization. */
+ /* 5.9.12.1 sets RCB timeout to be 25ms */
+ /* 5.9.12.2. RCB Cpl timeout on link down. */
+ set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
+ printk_info("rs780_gfx_init step5.9.12.1.\n");
+
+ /* step 5.9.12.3 disables slave ordering logic */
+ set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
+ printk_info("rs780_gfx_init step5.9.12.3.\n");
+
+ /* step 5.9.12.4 sets DMA payload size to 64 bytes */
+ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
+ /* 5.9.12.5. Blocks DMA traffic during C3 state. */
+ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+
+ /* 5.9.12.6. Disables RC ordering logic */
+ set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9);
+
+ /* Enabels TLP flushing. */
+ /* Note: It is got from RS690. The system will hang without this action. */
+ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
+
+ /* 5.9.12.7. Ignores DLLPs during L1 so that txclk can be turned off */
+ set_pcie_enable_bits(nb_dev, 0x2, 1 << 0, 1 << 0);
+
+ /* 5.9.12.8 Prevents LC to go from L0 to Rcv_L0s if L1 is armed. */
+ set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+
+ /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
+ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
+ printk_info("rs780_gfx_init step5.9.12.9.\n");
+
+ /* 5.9.12.10 Sets the timer in Config state from 20us to */
+ /* 5.9.12.11 De-asserts RX_EN in L0s. */
+ /* 5.9.12.12 Enables de-assertion of PG2RX_CR_EN to lock clock
+ * recovery parameter when lane is in electrical idle in L0s.*/
+ set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 << 23 | 1 << 19 | 1 << 28);
+
+ /* 5.9.12.13. Turns off offset calibration. */
+ /* 5.9.12.14. Enables Rx Clock gating in CDR */
+ set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 10/* | 1 << 22 */, 1 << 10/* | 1 << 22 */);
+
+ /* 5.9.12.15. Sets number of TX Clocks to drain TX Pipe to 3. */
+ set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 3 << 4);
+
+ /* 5.9.12.16. Lets PI use Electrical Idle from PHY when
+ * turning off PLL in L1 at Gen2 speed instead Inferred Electrical Idle. */
+ set_pcie_enable_bits(nb_dev, 0x40, 3 << 14, 2 << 14);
+
+ /* 5.9.12.17. Prevents the Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */
+ set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
+
+ /* 5.9.12.18. Prevents the LTSSM from going to Rcv_L0s if it has already
+ * acknowledged a request to go to L1. */
+ set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+
+ /* 5.9.12.19. LDSK only taking deskew on deskewing error detect */
+ set_pcie_enable_bits(nb_dev, 0x40, 1 << 28, 0 << 28);
+
+ /* 5.9.12.20. Bypasses lane de-skew logic if in x1 */
+ set_pcie_enable_bits(nb_dev, 0xC2, 1 << 14, 1 << 14);
+
+ /* 5.9.12.21. Sets Electrical Idle Threshold. */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 3 << 21, 2 << 21);
+
+ /* 5.9.12.22. Advertises -6 dB de-emphasis value in TS1 Data Rate Identifier
+ * Only if CMOS Option in section. skip */
+
+ /* 5.9.12.23. Disables GEN2 capability of the device. */
+ set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
+
+ /* 5.9.12.24.Disables advertising Upconfigure Support. */
+ set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
+
+ /* 5.9.12.25. No comment in RPR. */
+ set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 10, 0 << 10);
+
+ /* 5.9.12.26. This capacity is required since links wider than x1 and/or multiple link
+ * speed are supported */
+ set_pcie_enable_bits(nb_dev, 0xC1, 1 << 0, 1 << 0);
+
+ /* 5.9.12.27. Enables NVG86 ECO. A13 above only. */
+ if (get_nb_rev(nb_dev) == REV_RS780_A12) /* A12 */
+ set_pcie_enable_bits(dev, 0x02, 1 << 11, 1 << 11);
+
+ /* 5.9.12.28 Hides and disables the completion timeout method. */
+ set_pcie_enable_bits(nb_dev, 0xC1, 1 << 2, 0 << 2);
+
+ /* 5.9.12.29. Use the bif_core de-emphasis strength by default. */
+ /* set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 28, 1 << 28); */
+
+ /* 5.9.12.30. Set TX arbitration algorithm to round robin */
+ set_pcie_enable_bits(nb_dev, 0x1C,
+ 1 << 0 | 0x1F << 1 | 0x1F << 6,
+ 1 << 0 | 0x04 << 1 | 0x04 << 6);
+
+ /* Single-port/Dual-port configureation. */
+ switch (cfg->gfx_dual_slot) {
+ case 0:
+ single_port_configuration(nb_dev, dev);
+ break;
+ case 1:
+ dual_port_configuration(nb_dev, dev);
+ break;
+ default:
+ printk_info("Incorrect configuration of external gfx slot.\n");
+ break;
+ }
+}
diff --git a/src/southbridge/amd/rs780/rs780_ht.c b/src/southbridge/amd/rs780/rs780_ht.c
new file mode 100644
index 0000000000..5af19b1dcf
--- /dev/null
+++ b/src/southbridge/amd/rs780/rs780_ht.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "rs780.h"
+
+/* for UMA internal graphics */
+void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
+{
+ device_t cpu_f0;
+ u8 reg;
+
+ cpu_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21);
+
+ reg = nbpcie_p_read_index(sb_dev, 0x10);
+ reg |= 0x100; /* bit9=1 */
+ nbpcie_p_write_index(sb_dev, 0x10, reg);
+
+ reg = nbpcie_p_read_index(nb_dev, 0x10);
+ reg |= 0x100; /* bit9=1 */
+ nbpcie_p_write_index(nb_dev, 0x10, reg);
+
+ /* Enable NP protocol over PCIE for memory-mapped writes targeting LPC
+ * Set this bit to avoid a deadlock condition. */
+ reg = htiu_read_index(nb_dev, 0x6);
+ reg |= 0x1000000; /* bit26 */
+ htiu_write_index(nb_dev, 0x6, reg);
+}
+
+static void pcie_init(struct device *dev)
+{
+ /* Enable pci error detecting */
+ u32 dword;
+
+ printk_info("pcie_init in rs780_ht.c\n");
+
+ /* System error enable */
+ dword = pci_read_config32(dev, 0x04);
+ dword |= (1 << 8); /* System error enable */
+ dword |= (1 << 30); /* Clear possible errors */
+ pci_write_config32(dev, 0x04, dword);
+
+ /*
+ * 1 is APIC enable
+ * 18 is enable nb to accept A4 interrupt request from SB.
+ */
+ dword = pci_read_config32(dev, 0x4C);
+ dword |= 1 << 1 | 1 << 18; /* Clear possible errors */
+ pci_write_config32(dev, 0x4C, dword);
+}
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ht_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = pcie_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static struct pci_driver ht_driver __pci_driver = {
+ .ops = &ht_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_AMD_RS780_HT,
+};
diff --git a/src/southbridge/amd/rs780/rs780_pcie.c b/src/southbridge/amd/rs780/rs780_pcie.c
new file mode 100644
index 0000000000..b778af3aa6
--- /dev/null
+++ b/src/southbridge/amd/rs780/rs780_pcie.c
@@ -0,0 +1,449 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include "rs780.h"
+
+/*------------------------------------------------
+* Global variable
+------------------------------------------------*/
+PCIE_CFG AtiPcieCfg = {
+ PCIE_ENABLE_STATIC_DEV_REMAP, /* Config */
+ 0, /* ResetReleaseDelay */
+ 0, /* Gfx0Width */
+ 0, /* Gfx1Width */
+ 0, /* GfxPayload */
+ 0, /* GppPayload */
+ 0, /* PortDetect, filled by GppSbInit */
+ 0, /* PortHp */
+ 0, /* DbgConfig */
+ 0, /* DbgConfig2 */
+ 0, /* GfxLx */
+ 0, /* GppLx */
+ 0, /* NBSBLx */
+ 0, /* PortSlotInit */
+ 0, /* Gfx0Pwr */
+ 0, /* Gfx1Pwr */
+ 0 /* GppPwr */
+};
+
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
+static void ValidatePortEn(device_t nb_dev);
+
+static void ValidatePortEn(device_t nb_dev)
+{
+}
+
+/*****************************************************************
+* Compliant with CIM_33's PCIEPowerOffGppPorts
+* Power off unused GPP lines
+*****************************************************************/
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
+{
+ u32 reg;
+ u16 state_save;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+ u8 state = cfg->port_enable;
+
+ if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
+ state &= AtiPcieCfg.PortDetect;
+ state = ~state;
+ state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
+ state_save = state << 17;
+ state &= !(AtiPcieCfg.PortHp);
+ reg = nbmisc_read_index(nb_dev, 0x0c);
+ reg |= state;
+ nbmisc_write_index(nb_dev, 0x0c, reg);
+
+ reg = nbmisc_read_index(nb_dev, 0x08);
+ reg |= state_save;
+ nbmisc_write_index(nb_dev, 0x08, reg);
+
+ if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES)
+ && !(AtiPcieCfg.
+ Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
+ PCIE_GFX_COMPLIANCE))) {
+ }
+ /* step 3 Power Down Control for Southbridge */
+ reg = nbpcie_p_read_index(dev, 0xa2);
+
+ switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
+ case 1:
+ nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+ break;
+ case 2:
+ nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+ break;
+ default:
+ break;
+ }
+}
+
+static void pcie_init(struct device *dev)
+{
+ /* Enable pci error detecting */
+ u32 dword;
+
+ printk_debug("pcie_init in rs780_pcie.c\n");
+
+ /* System error enable */
+ dword = pci_read_config32(dev, 0x04);
+ dword |= (1 << 8); /* System error enable */
+ dword |= (1 << 30); /* Clear possible errors */
+ pci_write_config32(dev, 0x04, dword);
+}
+
+/**********************************************************************
+**********************************************************************/
+static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev)
+{
+ u32 reg;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+ /* 5.5.7.1-3 enables GPP reconfiguration */
+ reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+ reg |=
+ (RECONFIG_GPPSB_EN + RECONFIG_GPPSB_LINK_CONFIG +
+ RECONFIG_GPPSB_ATOMIC_RESET);
+ nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+ /* 5.5.7.4a. De-asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+ reg = nbmisc_read_index(nb_dev, 0x66);
+ reg |= 1 << 31;
+ nbmisc_write_index(nb_dev, 0x66, reg);
+ /* 5.5.7.4b. sets desired GPPSB configurations, bit4-7 */
+ reg = nbmisc_read_index(nb_dev, 0x67);
+ reg &= 0xFFFFff0f; /* clean */
+ reg |= cfg->gppsb_configuration << 4;
+ nbmisc_write_index(nb_dev, 0x67, reg);
+
+#if 1
+ /* NOTE:
+ * In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way,
+ * a x4 device in port B (dev 4) of Configuration B can only be detected
+ * as x1, instead of x4. When the port B is being trained, the
+ * LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. We have
+ * to set the PCIEIND:0x65 as 0xE0E0 and reset the slot. Then the card
+ * seems to work in x1 mode.
+ * In the 2nd way below, we do the 5 & 6 before 4c. it conforms the
+ * CIMx 4.3.0. It conflicts with RPR. But based on the test result I've
+ * made so far, I haven't found any mistake.
+ */
+ /* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+ reg = nbmisc_read_index(nb_dev, 0x66);
+ reg &= ~(1 << 31);
+ nbmisc_write_index(nb_dev, 0x66, reg);
+
+ /* 5.5.7.5-6. read bit14 and write back its inverst value */
+ reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+ reg ^= RECONFIG_GPPSB_GPPSB;
+ nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+#else
+ /* 5.5.7.5-6. read bit14 and write back its inverst value */
+ reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+ reg ^= RECONFIG_GPPSB_GPPSB;
+ nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+ /* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+ reg = nbmisc_read_index(nb_dev, 0x66);
+ reg &= ~(1 << 31);
+ nbmisc_write_index(nb_dev, 0x66, reg);
+#endif
+ /* 5.5.7.7. delay 1ms */
+ mdelay(1);
+
+ /* 5.5.7.8. waits until SB has trained to L0, poll for bit0-5 = 0x10 */
+ do {
+ reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0);
+ reg &= 0x3f; /* remain LSB [5:0] bits */
+ } while (LC_STATE_RECONFIG_GPPSB != reg);
+
+ /* 5.5.7.9.ensures that virtual channel negotiation is completed. poll for bit1 = 0 */
+ do {
+ reg =
+ pci_ext_read_config32(nb_dev, sb_dev,
+ PCIE_VC0_RESOURCE_STATUS);
+ } while (reg & VC_NEGOTIATION_PENDING);
+}
+
+static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
+{
+ u32 reg;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+ /* 5.6.2.1. De-asserts STRAP_BIF_all_valid for PCIE-GPP core */
+ reg = nbmisc_read_index(nb_dev, 0x22);
+ reg |= 1 << 14;
+ nbmisc_write_index(nb_dev, 0x22, reg);
+ /* 5.6.2.2. sets desired GPPSB configurations, bit4-7 */
+ reg = nbmisc_read_index(nb_dev, 0x2D);
+ reg &= ~(0xF << 7); /* clean */
+ reg |= cfg->gpp_configuration << 7;
+ nbmisc_write_index(nb_dev, 0x2D, reg);
+ /* 5.6.2.3. Asserts STRAP_BIF_all_valid for PCIE-GPP core */
+ reg = nbmisc_read_index(nb_dev, 0x22);
+ reg &= ~(1 << 14);
+ nbmisc_write_index(nb_dev, 0x22, reg);
+}
+
+/*****************************************************************
+* The rs780 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
+* Space to a 256MB range within the first 4GB of addressable memory.
+*****************************************************************/
+void enable_pcie_bar3(device_t nb_dev)
+{
+ printk_debug("enable_pcie_bar3()\n");
+ set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
+ set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
+
+ pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */
+ pci_write_config32(nb_dev, 0x20, 0x00000000);
+ set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
+ ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************************************
+* We should disable bar3 when we want to exit rs780_enable, because bar3 will be
+* remapped in set_resource later.
+*****************************************************************/
+void disable_pcie_bar3(device_t nb_dev)
+{
+ printk_debug("disable_pcie_bar3()\n");
+ pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
+ set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */
+ ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEGPPInit
+* nb_dev:
+* root bridge struct
+* dev:
+* p2p bridge struct
+* port:
+* p2p bridge number, 4-10
+*****************************************/
+void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
+{
+ u8 reg8;
+ u16 reg16;
+ device_t sb_dev;
+ u32 gfx_gpp_sb_sel;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+ printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port);
+
+ gfx_gpp_sb_sel = port >= 4 && port <= 8 ?
+ PCIE_CORE_INDEX_GPPSB : /* 4,5,6,7,8 */
+ PCIE_CORE_INDEX_GPP; /* 9,10 */
+ /* init GPP core */
+ /* 5.10.8.3. Disable slave ordering logic */
+ set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 8,
+ 1 << 8);
+ /* 5.10.8.7. PCIE initialization 5.10.2: rpr 2.12*/
+ set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0); /* no description in datasheet. */
+
+ /* init GPPSB port. rpr 5.10.8 */
+ /* 5.10.8.1-5.10.8.2. Sets RCB timeout to be 100ms/4=25ms by setting bits[18:16] to 3 h4
+ * and shortens the enumeration timer by setting bit[19] to 1
+ */
+ set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0x4 << 16 | 1 << 19);
+ /* 5.10.8.4. Sets DMA payload size to 64 bytes. */
+ set_pcie_enable_bits(nb_dev, 0x10 | gfx_gpp_sb_sel, 7 << 10, 4 << 10);
+ /* 5.10.8.6. Disable RC ordering logic */
+ set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 9, 1 << 9);
+ /* 5.10.8.7. Ignores DLLs druing L1 */
+ set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0);
+ /* 5.10.8.8. Prevents LCto go from L0 to Rcv_L0s if L1 is armed. */
+ set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+ /* 5.10.8.9. Sets timer in Config state from 20us to 1us.
+ * 5.10.8.10. De-asserts RX_EN in L0s
+ * 5.10.8.11. Enables de-assertion of PG2RX_CR_EN to lock clock recovery parameter when .. */
+ set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 <<23 | 1 << 19 | 1 << 28);
+ /* 5.10.8.12. Turns off offset calibration */
+ /* 5.10.8.13. Enables Rx Clock gating in CDR */
+ if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+ set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 14 | 1 << 26, 1 << 14 | 1 << 26); /* 4,5,6,7 */
+ else
+ set_nbmisc_enable_bits(nb_dev, 0x24, 1 << 29 | 1 << 28, 1 << 29 | 1 << 28); /* 9,10 */
+ /* 5.10.8.14. Sets number of TX Clocks to drain TX Pipe to 3 */
+ set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4);
+ /* 5.10.8.15. empty */
+ /* 5.10.8.16. P_ELEC_IDLE_MODE */
+ set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 0x3 << 14, 0x2 << 14);
+ /* 5.10.8.17. LC_BLOCK_EL_IDLE_IN_L0 */
+ set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
+ /* 5.10.8.18. LC_DONT_GO_TO_L0S_IFL1_ARMED */
+ set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+ /* 5.10.8.19. RXP_REALIGN_ON_EACH_TSX_OR_SKP */
+ set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 1 << 28, 0 << 28);
+ /* 5.10.8.20. Bypass lane de-skew logic if in x1 */
+ set_pcie_enable_bits(nb_dev, 0xC2 | gfx_gpp_sb_sel, 1 << 14, 1 << 14);
+ /* 5.10.8.21. sets electrical idle threshold. */
+ if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+ set_nbmisc_enable_bits(nb_dev, 0x6A, 3 << 22, 2 << 22);
+ else
+ set_nbmisc_enable_bits(nb_dev, 0x24, 3 << 16, 2 << 16);
+
+ /* 5.10.8.22. Disable GEN2 */
+ /* TODO: should be 2 seperated cases. */
+ set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0 << 31);
+ set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 5, 0 << 5);
+ set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 31, 0 << 31);
+ set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 5, 0 << 5);
+ /* 5.10.8.23. Disables GEN2 capability of the device. RPR says enable? No! */
+ set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
+ /* 5.10.8.24. Disable advertising upconfigure support. */
+ set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
+ /* 5.10.8.25-26. STRAP_BIF_DSN_EN */
+ if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+ set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 19, 0 << 19);
+ else
+ set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 3, 0 << 3);
+ /* 5.10.8.27-28. */
+ set_pcie_enable_bits(nb_dev, 0xC1 | gfx_gpp_sb_sel, 1 << 0 | 1 << 2, 1 << 0 | 0 << 2);
+ /* 5.10.8.29. Uses the bif_core de-emphasis strength by default. */
+ if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) {
+ set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10, 1 << 10);
+ set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 29, 1 << 29);
+ }
+ else {
+ set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 30, 1 << 30);
+ }
+ /* 5.10.8.30. Set TX arbitration algorithm to round robin. */
+ set_pcie_enable_bits(nb_dev, 0x1C | gfx_gpp_sb_sel,
+ 1 << 0 | 0x1F << 1 | 0x1F << 6,
+ 1 << 0 | 0x04 << 1 | 0x04 << 6);
+
+ /* check compliance rpr step 2.1*/
+ if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) {
+ u32 tmp;
+ tmp = nbmisc_read_index(nb_dev, 0x67);
+ tmp |= 1 << 3;
+ nbmisc_write_index(nb_dev, 0x67, tmp);
+ }
+
+ /* step 5: dynamic slave CPL buffer allocation. Disable it, otherwise linux hangs. Why? */
+ /* set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 11, 1 << 11); */
+
+ /* step 5a: Training for GPP devices */
+ /* init GPP */
+ switch (port) {
+ case 4: /* GPP */
+ case 5:
+ case 6:
+ case 7:
+ case 9:
+ case 10:
+ /* 5.10.8.5. Blocks DMA traffic during C3 state */
+ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+ /* Enabels TLP flushing */
+ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
+
+ /* check port enable */
+ if (cfg->port_enable & (1 << port)) {
+ PcieReleasePortTraining(nb_dev, dev, port);
+ if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
+ u8 res = PcieTrainPort(nb_dev, dev, port);
+ printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res);
+ if (res) {
+ AtiPcieCfg.PortDetect |= 1 << port;
+ }
+ }
+ }
+ break;
+ case 8: /* SB */
+ break;
+ }
+ PciePowerOffGppPorts(nb_dev, dev, port);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEConfigureGPPCore
+*****************************************/
+void config_gpp_core(device_t nb_dev, device_t sb_dev)
+{
+ u32 reg;
+ struct southbridge_amd_rs780_config *cfg =
+ (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+ reg = nbmisc_read_index(nb_dev, 0x20);
+ if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
+ reg &= 0xfffffffd; /* set bit1 = 0 */
+ else
+ reg |= 0x2; /* set bit1 = 1 */
+ nbmisc_write_index(nb_dev, 0x20, reg);
+
+ reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG_GPPSB at bit 4-7 */
+ if (cfg->gppsb_configuration != ((reg >> 4) & 0xf))
+ switching_gppsb_configurations(nb_dev, sb_dev);
+ reg = nbmisc_read_index(nb_dev, 0x2D); /* get STRAP_BIF_LINK_CONFIG_GPP at bit 7-10 */
+ if (cfg->gpp_configuration != ((reg >> 7) & 0xf))
+ switching_gpp_configurations(nb_dev, sb_dev);
+ ValidatePortEn(nb_dev);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEMiscClkProg
+*****************************************/
+void pcie_config_misc_clk(device_t nb_dev)
+{
+ u32 reg;
+ struct bus pbus; /* fake bus for dev0 fun1 */
+
+ reg = pci_read_config32(nb_dev, 0x4c);
+ reg |= 1 << 0;
+ pci_write_config32(nb_dev, 0x4c, reg);
+
+ if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
+ /* TXCLK Clock Gating */
+ set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
+ set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
+ set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
+
+ /* LCLK Clock Gating */
+ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg &= ~(1 << 16);
+ pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+ }
+
+ if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
+ /* TXCLK Clock Gating */
+ set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4);
+ set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
+ set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6);
+
+ /* LCLK Clock Gating */
+ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg &= ~(1 << 24);
+ pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+ }
+
+ reg = pci_read_config32(nb_dev, 0x4c);
+ reg &= ~(1 << 0);
+ pci_write_config32(nb_dev, 0x4c, reg);
+}
diff --git a/src/southbridge/amd/rs780/rs780_rev.h b/src/southbridge/amd/rs780/rs780_rev.h
new file mode 100644
index 0000000000..94ab752f9f
--- /dev/null
+++ b/src/southbridge/amd/rs780/rs780_rev.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __RS780_REV_H__
+#define __RS780_REV_H__
+
+#define REV_RS780_A11 0
+#define REV_RS780_A12 1
+#define REV_RS780_A13 2
+
+#endif /* __RS780_REV_H__ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 06:58:22 +0000