x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

4 files changed, 16 insertions, 16 deletions

diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c
index c65f324832..de7a31913f 100644
--- a/src/southbridge/amd/sb600/hda.c
+++ b/src/southbridge/amd/sb600/hda.c
@@ -30,7 +30,7 @@
 #define HDA_ICII_BUSY (1 << 0)
 #define HDA_ICII_VALID (1 << 1)
 
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
 {
 	u32 dword;
 	int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
 	return 0;
 }
 
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
 {
 	u32 dword;
 
@@ -172,7 +172,7 @@ static u32 find_verb(u32 viddid, u32 ** verb)
  *  Wait 50usec for the codec to indicate it is ready
  *  no response would imply that the codec is non-operative
  */
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -194,7 +194,7 @@ static int wait_for_ready(u32 base)
  *  the previous command.  No response would imply that the code
  *  is non-operative
  */
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -211,7 +211,7 @@ static int wait_for_valid(u32 base)
 	return -1;
 }
 
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
 {
 	u32 dword;
 	u32 *verb;
@@ -253,7 +253,7 @@ static void codec_init(u32 base, int addr)
 	printk(BIOS_DEBUG, "verb loaded!\n");
 }
 
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
 {
 	int i;
 	for (i = 2; i >= 0; i--) {
@@ -266,7 +266,7 @@ static void hda_init(struct device *dev)
 {
 	u8 byte;
 	u32 dword;
-	u32 base;
+	void *base;
 	struct resource *res;
 	u32 codec_mask;
 	device_t sm_dev;
@@ -300,8 +300,8 @@ static void hda_init(struct device *dev)
 	if (!res)
 		return;
 
-	base = (u32)res->base;
-	printk(BIOS_DEBUG, "base = 0x%x\n", base);
+	base = res2mmio(res, 0, 0);
+	printk(BIOS_DEBUG, "base = 0x%p\n", base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index a17aab8df7..2ff718230a 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -63,7 +63,7 @@ static void sata_init(struct device *dev)
 	u8 byte;
 	u16 word;
 	u32 dword;
-	u32 sata_bar5;
+	void *sata_bar5;
 	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
 	int i, j;
 
@@ -88,7 +88,7 @@ static void sata_init(struct device *dev)
 	pci_write_config8(sm_dev, 0xaf, byte);
 
 	/* get base address */
-	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+	sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
 	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
 	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
 	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -100,7 +100,7 @@ static void sata_init(struct device *dev)
 	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
 	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
 	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+	printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5);	/* e0309000 */
 
 	/* SERR-Enable */
 	word = pci_read_config16(dev, 0x04);
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index a8e72c28f7..3ce5f020fa 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -57,7 +57,7 @@ static void sm_init(device_t dev)
 
 	ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0);	/* some like mem resource, but does not have  enable bit */
 	/* Don't rename APIC ID */
-	clear_ioapic(ioapic_base);
+	clear_ioapic((void *)ioapic_base);
 
 	dword = pci_read_config8(dev, 0x62);
 	dword |= 1 << 2;
diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c
index 137a8dac61..1b2b9ff1ae 100644
--- a/src/southbridge/amd/sb600/usb.c
+++ b/src/southbridge/amd/sb600/usb.c
@@ -88,13 +88,13 @@ static void usb_init2(struct device *dev)
 	u8 byte;
 	u16 word;
 	u32 dword;
-	u32 usb2_bar0;
+	void *usb2_bar0;
 	/* dword = pci_read_config32(dev, 0xf8); */
 	/* dword |= 40; */
 	/* pci_write_config32(dev, 0xf8, dword); */
 
-	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
-	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+	usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+	printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
 
 	/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
 	dword = 0x00020F00;