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authorZheng Bao <zheng.bao@amd.com>2010-03-17 03:10:39 +0000
committerZheng Bao <Zheng.Bao@amd.com>2010-03-17 03:10:39 +0000
commitd4e77df5797361db39058f478ee300e9638435f9 (patch)
tree6ee826beeaeeee44d4e60b13879ea06afeebc7fd /src/southbridge/amd/sb600
parent68f542cdf82efe257ee4251047a264558dd8645f (diff)
downloadcoreboot-d4e77df5797361db39058f478ee300e9638435f9.tar.xz
The SB600 also has the BootFailTimer. We should disable it,
otherwise it will keeps reboot. The comment was also added in detail to make less confusing when we debug SB600/SB700. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/sb600')
-rw-r--r--src/southbridge/amd/sb600/sb600_early_setup.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c
index 7bb910a4b8..29c215adba 100644
--- a/src/southbridge/amd/sb600/sb600_early_setup.c
+++ b/src/southbridge/amd/sb600/sb600_early_setup.c
@@ -71,8 +71,16 @@ static void sb600_lpc_init(void)
u32 reg32;
device_t dev;
- /* Enable lpc controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
+ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
+ * This bit has no meaning if debug strap is not enabled. So if the
+ * board keeps rebooting and the code fails to reach here, we could
+ * disable the debug strap first. */
+ reg32 = pci_read_config32(dev, 0x4C);
+ reg32 |= 1 << 31;
+ pci_write_config32(dev, 0x4C, reg32);
+
+ /* Enable lpc controller */
reg32 = pci_read_config32(dev, 0x64);
reg32 |= 1 << 20;
pci_write_config32(dev, 0x64, reg32);