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| author | Martin Roth <martinroth@google.com> | 2016-08-31 12:44:14 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 21:16:06 +0200 |
| commit | a795ae1392327a17d37193834271883743b21311 (patch) | |
| tree | bed189275e562fc0d92f54c41fddbb7f07af4325 /src/southbridge/amd/sb700/Kconfig | |
| parent | 61e6c4448c4d79035842434fb1eb3b4e9cd01c6d (diff) | |
| download | coreboot-a795ae1392327a17d37193834271883743b21311.tar.xz | |
amd/sb700/bootblock.c: Restore accidentally deleted code
The recent changes to this file from commit 6e5421d2
(sb/amd/sb700: Add option to increase SPI speed to 33MHz)
were accidentally removed in a code cleanup patch:
commit ba28e8d7 (src/southbridge: Code formating).
Change-Id: I6cf3e8f29d5c0384d35637f35e051be40318d20f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16384
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/sb700/Kconfig')
| -rw-r--r-- | src/southbridge/amd/sb700/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 9a988a90f8..353c2a46c7 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -25,6 +25,16 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS +config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI + bool "Enable high speed SPI clock" + default n + help + When set, the SPI clock will run at 33MHz instead + of the compatibility mode 16.5MHz. Note that not + all ROMs are capable of 33MHz operation, so you + will need to verify this option is appropriate for + the ROM you are using. + # Set for southbridge SP5100 which also uses SB700 driver config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool |