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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-31 19:22:16 +0200
committerMartin Roth <martinroth@google.com>2016-08-31 20:22:46 +0200
commitba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch)
tree9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/amd/sb700/Kconfig
parent2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff)
downloadcoreboot-ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1.tar.xz
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/sb700/Kconfig')
-rw-r--r--src/southbridge/amd/sb700/Kconfig10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 353c2a46c7..9a988a90f8 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET
select SMBUS_HAS_AUX_CHANNELS
-config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
- bool "Enable high speed SPI clock"
- default n
- help
- When set, the SPI clock will run at 33MHz instead
- of the compatibility mode 16.5MHz. Note that not
- all ROMs are capable of 33MHz operation, so you
- will need to verify this option is appropriate for
- the ROM you are using.
-
# Set for southbridge SP5100 which also uses SB700 driver
config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
bool