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| author | Rudolf Marek <r.marek@assembler.cz> | 2011-01-28 20:57:48 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2011-01-28 20:57:48 +0000 |
| commit | 86bd99aba2cec223df48c2a00bdea0450f6346e0 (patch) | |
| tree | 0b8aecef2fe7ce84aafa08ca2dc4e3ca1e10d79c /src/southbridge/amd/sb700/lpc.c | |
| parent | 16ce01b0d8414a7250fcf142a966ff22c153e85f (diff) | |
| download | coreboot-86bd99aba2cec223df48c2a00bdea0450f6346e0.tar.xz | |
Attached patch fixes the LPC decode ranges of SB700. We enable early only Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/sb700/lpc.c')
| -rw-r--r-- | src/southbridge/amd/sb700/lpc.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a08780e521..fda99d6e38 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -140,7 +140,8 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) struct bus *link; u32 reg, reg_x; int var_num = 0; - u16 reg_var[3]; + u16 reg_var[3] = {0x0, 0x0, 0x0}; + u8 wiosize = pci_read_config8(dev, 0x74); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); @@ -171,13 +172,14 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) case 0x2f8: /* COM2 */ reg |= (1 << 7); break; - case 0x378: /* Parallal 1 */ + case 0x378: /* Parallel 1 */ reg |= (1 << 0); + reg |= (1 << 1); /* + 0x778 for ECP */ break; case 0x3f0: /* FD0 */ reg |= (1 << 26); break; - case 0x220: /* Aduio 0 */ + case 0x220: /* Audio 0 */ reg |= (1 << 8); break; case 0x300: /* Midi 0 */ @@ -207,12 +209,19 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) switch (var_num) { case 0: reg_x |= (1 << 2); + if ((end - base) < 16) + wiosize |= (1 << 0); break; case 1: reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 2); break; case 2: reg_x |= (1 << 25); + reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 3); break; } reg_var[var_num++] = @@ -234,6 +243,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) pci_write_config16(dev, 0x64, reg_var[0]); break; } + pci_write_config8(dev, 0x74, wiosize); } static void sb700_lpc_enable_resources(device_t dev) |