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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 17:23:12 +0100 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-20 19:01:05 +0000 |
commit | 24284270c73ba4e35af10ea9054f084c989dff52 (patch) | |
tree | e9a61270217da63a4ca1e849c1dee7cda0fadd58 /src/southbridge/amd/sb700/reset.c | |
parent | ecebee0561cf3e06bfba55509a5b7bebdb54d998 (diff) | |
download | coreboot-24284270c73ba4e35af10ea9054f084c989dff52.tar.xz |
sb/amd/sb700: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.
Change-Id: Iffa4f54b2d1b43b6710447e69061c6ed433bff1d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36967
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/sb700/reset.c')
-rw-r--r-- | src/southbridge/amd/sb700/reset.c | 66 |
1 files changed, 0 insertions, 66 deletions
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c deleted file mode 100644 index 9a04459799..0000000000 --- a/src/southbridge/amd/sb700/reset.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 - 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <reset.h> -#include <southbridge/amd/common/reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - pci_devfn_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void do_board_reset(void) -{ - set_bios_reset(); - - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset - * --- it only reset coherent link table, but not reset link freq and width - */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} |