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| author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 12:37:58 -0600 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 00:20:59 +0200 |
| commit | 00c8c4a31632150fa711493f39e727da950ebe9f (patch) | |
| tree | f3bad2e78ddb6999ad551a73f05c049a266a14ab /src/southbridge/amd/sb700/sb700.h | |
| parent | 09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff) | |
| download | coreboot-00c8c4a31632150fa711493f39e727da950ebe9f.tar.xz | |
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sb700/sb700.h')
| -rwxr-xr-x[-rw-r--r--] | src/southbridge/amd/sb700/sb700.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index 60eea47ee7..794dd96a81 100644..100755 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -63,8 +63,11 @@ void sb7xx_51xx_enable(device_t dev); #ifdef __PRE_RAM__ void sb7xx_51xx_lpc_port80(void); void sb7xx_51xx_pci_port80(void); +void sb7xx_51xx_lpc_init(void); void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base); void sb7xx_51xx_disable_wideio(u8 wio_index); +void sb7xx_51xx_early_setup(void); +void sb7xx_51xx_before_pci_init(void); #else #include <device/pci.h> /* allow override in mainboard.c */ @@ -72,8 +75,15 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev); #endif +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_is_wakeup_early(void); +#endif + int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void enable_usbdebug(unsigned int port); + +u32 __attribute__ ((weak)) get_sbdn(u32 bus); +void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn); #endif /* SB700_H */ |