diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-05 13:40:31 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-05 13:40:31 +0000 |
| commit | 5692c5733633bfb8b23f1111de152eff0233b713 (patch) | |
| tree | d315817986c71d6710f75dceb87689b95e1bff53 /src/southbridge/amd/sb700 | |
| parent | d0835953506263b0d9218b62176693315f2ef2f3 (diff) | |
| download | coreboot-5692c5733633bfb8b23f1111de152eff0233b713.tar.xz | |
- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/sb700')
| -rw-r--r-- | src/southbridge/amd/sb700/Kconfig | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sb700.h | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sb700_enable_usbdebug.c | 13 |
4 files changed, 16 insertions, 7 deletions
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 5ceb446a82..97768d18e5 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -27,3 +27,11 @@ config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT default n depends on SOUTHBRIDGE_AMD_SB700 +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB700 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB700 + diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 8e6868bb17..dd97df31e6 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -7,3 +7,4 @@ driver-y += sb700_sata.c driver-y += sb700_hda.c driver-y += sb700_pci.c ramstage-y += sb700_reset.c +romstage-y += sb700_enable_usbdebug.c diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index d4107a942e..088bba611d 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -59,4 +59,5 @@ void sb700_setup_sata_phys(struct device *dev); #endif +void sb700_enable_usbdebug(unsigned int port); #endif /* SB700_H */ diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c index 02d3900047..d74a9bbc9f 100644 --- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c +++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c @@ -19,14 +19,13 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "sb700.h" -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ - -#define EHCI_EOR (EHCI_BAR + 0x20) +#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) void set_debug_port(unsigned int port) @@ -46,12 +45,12 @@ void set_debug_port(unsigned int port) * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ -static void sb700_enable_usbdebug(unsigned int port) +void sb700_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |