diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-22 02:18:00 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-01-06 01:17:54 +0000 |
| commit | c70eed1e6202c928803f3e7f79161cd247a62b23 (patch) | |
| tree | e46a6c87f6f13b7719fd40a9360d8d03359bfffb /src/southbridge/amd/sb700 | |
| parent | 54efaae701dacd58621e66a8cf56812eb5304946 (diff) | |
| download | coreboot-c70eed1e6202c928803f3e7f79161cd247a62b23.tar.xz | |
device: Use pcidev_on_root()
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/amd/sb700')
| -rw-r--r-- | src/southbridge/amd/sb700/ide.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sata.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/spi.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/usb.c | 4 |
5 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index d08f2f1cb2..673464318c 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -56,7 +56,7 @@ static void ide_init(struct device *dev) /* set ide as primary, if you want to boot from IDE, you'd better set it * in $vendor/$mainboard/devicetree.cb */ if (conf->boot_switch_sata_ide == 1) { - struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + struct device *sm_dev = pcidev_on_root(0x14, 0); byte = pci_read_config8(sm_dev, 0xad); byte |= 1 << 4; pci_write_config8(sm_dev, 0xad, byte); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 857503a7ed..eb0af0de1c 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -40,7 +40,7 @@ static void lpc_init(struct device *dev) printk(BIOS_SPEW, "%s\n", __func__); /* Enable the LPC Controller */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 975e5ac132..f1c05f62f6 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -134,7 +134,7 @@ static void sata_init(struct device *dev) struct device *sm_dev; /* SATA SMBus Disable */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* WARNING * Enabling the SATA link latency enhancement (SMBUS 0xAD bit 5) @@ -171,7 +171,7 @@ static void sata_init(struct device *dev) struct device *ide_dev; /* IDE Device */ - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + ide_dev = pcidev_on_root(0x14, 1); /* Disable legacy IDE mode (enable PATA_BAR0/2) */ byte = pci_read_config8(ide_dev, 0x09); diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 1fa29aa817..8dc142db45 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -31,7 +31,7 @@ static uint32_t get_spi_bar(void) { struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + dev = pcidev_on_root(0x14, 3); return pci_read_config32(dev, 0xa0) & ~0x1f; } diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index bf790565ee..3ca12f6866 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -35,7 +35,7 @@ static void usb_init(struct device *dev) /* 6.1 Enable OHCI0-4 and EHCI Controllers */ struct device *sm_dev; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); byte = pci_read_config8(sm_dev, 0x68); byte |= 0xFF; pci_write_config8(sm_dev, 0x68, byte); @@ -88,7 +88,7 @@ static void usb_init2(struct device *dev) if (get_option(&nvram, "ehci_async_data_cache") == CB_SUCCESS) ehci_async_data_cache = !!nvram; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); rev = get_sb700_revision(sm_dev); /* dword = pci_read_config32(dev, 0xf8); */ |