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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-10-25 18:58:24 -0500
committerMartin Roth <martinroth@google.com>2015-12-01 16:59:41 +0100
commit1a38374535df694a1a63d1f198d9828249019390 (patch)
tree8a7448f4d668b9c6105e1d1e4cfd2aee2cbde33d /src/southbridge/amd/sb700
parent273384638b4f4fbe8e500025d8941bd2e54b5f8a (diff)
downloadcoreboot-1a38374535df694a1a63d1f198d9828249019390.tar.xz
southbridge/amd/sb700: Fix boot hang when AHCI mode disabled
Existence of requested PCI device was not checked when enabling IDE mode on the SP5100. Fix incorrect PCI device ID and check for device existence before attempting setup. Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12572 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/sb700')
-rw-r--r--src/southbridge/amd/sb700/early_setup.c32
1 files changed, 17 insertions, 15 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index f7e91207f5..06c6c77365 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -520,26 +520,28 @@ static void sb700_devices_por_init(void)
if (!sata_ahci_mode){
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
/* SP5100 default SATA mode is RAID5 MODE */
- dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0);
+ dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0);
- /* Set SATA Operation Mode, Set to IDE mode */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 0);
- pci_write_config8(dev, 0x40, byte);
+ if (dev != PCI_DEV_INVALID) {
+ /* Set SATA Operation Mode, Set to IDE mode */
+ byte = pci_read_config8(dev, 0x40);
+ byte |= (1 << 0);
+ pci_write_config8(dev, 0x40, byte);
- dword = 0x01018f00;
- pci_write_config32(dev, 0x8, dword);
+ dword = 0x01018f00;
+ pci_write_config32(dev, 0x8, dword);
- /* set SATA Device ID writable */
- dword = pci_read_config32(dev, 0x40);
- dword &= ~(1 << 24);
- pci_write_config32(dev, 0x40, dword);
+ /* set SATA Device ID writable */
+ dword = pci_read_config32(dev, 0x40);
+ dword &= ~(1 << 24);
+ pci_write_config32(dev, 0x40, dword);
- /* set Device ID consistent with IDE emulation mode configuration */
- pci_write_config32(dev, 0x0, 0x43901002);
+ /* set Device ID consistent with IDE emulation mode configuration */
+ pci_write_config32(dev, 0x0, 0x43901002);
- /* rpr v2.13 4.17 Reset CPU on Sync Flood */
- abcfg_reg(0x10050, 1 << 2, 1 << 2);
+ /* rpr v2.13 4.17 Reset CPU on Sync Flood */
+ abcfg_reg(0x10050, 1 << 2, 1 << 2);
+ }
#endif
}