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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-18 19:18:56 +0200
committerMartin Roth <martinroth@google.com>2016-09-20 17:15:32 +0200
commitc021ffee45f7b19b3a8e6c426e0d14a4609bf593 (patch)
tree6c6a5667ccd217f5272f178271d360947eae1231 /src/southbridge/amd/sb700
parentbf7faa1a634e8bed0d0a8b6634dfe10f42ab986c (diff)
downloadcoreboot-c021ffee45f7b19b3a8e6c426e0d14a4609bf593.tar.xz
southbridge/amd: Add space around operators
Change-Id: I949ff7de072e5e0753d9c8ff0bf98abfca25798b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16637 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/sb700')
-rw-r--r--src/southbridge/amd/sb700/early_setup.c6
-rw-r--r--src/southbridge/amd/sb700/enable_usbdebug.c2
-rw-r--r--src/southbridge/amd/sb700/hda.c2
-rw-r--r--src/southbridge/amd/sb700/lpc.c2
-rw-r--r--src/southbridge/amd/sb700/reset.c2
5 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 1aa7be0cd6..ea7eb27161 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -814,7 +814,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
int i;
printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
- for (i = 0; i<size; i++) {
+ for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
nvram_pos++;
@@ -827,7 +827,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
{
u32 data = *old_dword;
int i;
- for (i = 0; i<size; i++) {
+ for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
data &= ~(0xff << (i * 8));
data |= inb(BIOSRAM_DATA) << (i *8);
@@ -865,7 +865,7 @@ unsigned long get_top_of_ram(void)
int xnvram_pos = 0xfc, xi;
if (acpi_get_sleep_type() != 3)
return 0;
- for (xi = 0; xi<4; xi++) {
+ for (xi = 0; xi < 4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 2b0f8cc7a6..22f730f4ed 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -27,7 +27,7 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
- if (hcd_idx==2)
+ if (hcd_idx == 2)
return PCI_DEV(0, 0x13, 2);
else
return PCI_DEV(0, 0x12, 2);
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index 8497cc5da2..22537222ec 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -98,7 +98,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
while (timeout--) {
- u32 dword=read32(base + HDA_ICII_REG);
+ u32 dword = read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
udelay(1);
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index f138d88d72..7b53820e0f 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -93,7 +93,7 @@ void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = (u32) ramtop;
int nvram_pos = 0xfc, i;
- for (i = 0; i<4; i++) {
+ for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
nvram_pos++;
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index d0cd4a42f0..3c44982e6a 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -23,7 +23,7 @@
#define HTIC_BIOSR_Detect (1<<5)
#if CONFIG_MAX_PHYSICAL_CPUS > 32
-#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
#endif