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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-05 23:10:48 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-07 18:56:33 +0200 |
| commit | 2268e0dc15d076c61792b97e954cad3f7c5f8c00 (patch) | |
| tree | be2573ad5c5adfd521600c8240d80a5d9e36a434 /src/southbridge/amd/sb700 | |
| parent | 2fe2d3d7752bd65f87c4bada85853bf29c4278ba (diff) | |
| download | coreboot-2268e0dc15d076c61792b97e954cad3f7c5f8c00.tar.xz | |
sb/amd/sb700: Enable reset on sync flood
The logic to enable reset on sync flood per RPR guidelines
somehow ended up guarded on the SATA AHCI setup. Unconditionally
enable reset on sync flood per the RPR.
Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14260
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/amd/sb700')
| -rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 76855fba34..8042849007 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -543,13 +543,13 @@ static void sb700_devices_por_init(void) /* set Device ID consistent with IDE emulation mode configuration */ pci_write_config32(dev, 0x0, 0x43901002); - - /* rpr v2.13 4.17 Reset CPU on Sync Flood */ - abcfg_reg(0x10050, 1 << 2, 1 << 2); } #endif } + /* rpr v2.13 4.17 Reset CPU on Sync Flood */ + abcfg_reg(0x10050, 1 << 2, 1 << 2); + /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-17-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0); |