summaryrefslogtreecommitdiff
path: root/src/southbridge/amd/sb700
diff options
context:
space:
mode:
authorMartin Roth <martinroth@google.com>2017-06-24 21:30:14 -0600
committerMartin Roth <martinroth@google.com>2017-06-30 03:44:59 +0000
commit083504b66b5f3b281221f0a8f4fd62a4d9071287 (patch)
treedcf6fcb31f5d7ee760634c86b0fc06a7383e6d94 /src/southbridge/amd/sb700
parent5f9c6734fc9bbe69c007c46c8ec6f314bd5522a8 (diff)
downloadcoreboot-083504b66b5f3b281221f0a8f4fd62a4d9071287.tar.xz
southbridge/amd: add IS_ENABLED() around Kconfig symbol references
Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sb700')
-rw-r--r--src/southbridge/amd/sb700/early_setup.c8
-rw-r--r--src/southbridge/amd/sb700/lpc.c4
-rw-r--r--src/southbridge/amd/sb700/sata.c2
-rw-r--r--src/southbridge/amd/sb700/sb700.c2
-rw-r--r--src/southbridge/amd/sb700/usb.c2
5 files changed, 9 insertions, 9 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 3ed4cac8a1..0cd65a6f54 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -152,7 +152,7 @@ void sb7xx_51xx_lpc_init(void)
reg32 |= 1 << 20;
pci_write_config32(dev, 0x64, reg32);
-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
post_code(0x66);
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
reg8 = pci_read_config8(dev, 0xBB);
@@ -166,7 +166,7 @@ void sb7xx_51xx_lpc_init(void)
// XXX Serial port decode on LPC is hardcoded to 0x3f8
reg8 = pci_read_config8(dev, 0x44);
reg8 |= 1 << 6;
-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG_TTYS0_BASE == 0x2f8
reg8 |= 1 << 7;
#endif
@@ -532,7 +532,7 @@ static void sb700_devices_por_init(void)
pci_write_config8(dev, 0x50, 0x01);
if (!sata_ahci_mode){
-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* SP5100 default SATA mode is RAID5 MODE */
dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0);
@@ -688,7 +688,7 @@ static void sb700_pmio_por_init(void)
byte |= 0xc0;
pmio_write(0xbb, byte);
-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* RPR 2.26 Alter CPU reset timing */
byte = pmio_read(0xb2);
byte |= 0x1 << 2; /* Enable CPU reset timing option */
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index fda30b8687..8ee0395ccd 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -47,7 +47,7 @@ static void lpc_init(device_t dev)
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
-#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT)
printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
#else
isa_dma_init();
@@ -68,7 +68,7 @@ static void lpc_init(device_t dev)
/* Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* Disable FlowContrl, Always service the request from Host
* whenever there is a request from Host pending
*/
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 235278da16..537c2c08b4 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -350,7 +350,7 @@ static void sata_init(struct device *dev)
byte |= 7 << 0;
pci_write_config8(dev, 0x4, byte);
-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* Master Latency Timer */
pci_write_config32(dev, 0xC, 0x00004000);
#endif
diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c
index 74650e7277..10687217fa 100644
--- a/src/southbridge/amd/sb700/sb700.c
+++ b/src/southbridge/amd/sb700/sb700.c
@@ -222,7 +222,7 @@ void sb7xx_51xx_enable(device_t dev)
}
}
-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
struct chip_operations southbridge_amd_sb700_ops = {
CHIP_NAME("ATI SP5100")
.enable_dev = sb7xx_51xx_enable,
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index 0fdff78f44..627600823e 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -181,7 +181,7 @@ static void usb_init2(struct device *dev)
dword |= 1 << 8;
dword &= ~(1 << 27); /* 6.23 */
}
-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* SP5100 Erratum 36 */
dword &= ~(1 << 26);
if (!ehci_async_data_cache)