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| author | Nico Huber <nico.huber@secunet.com> | 2012-10-02 11:11:42 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-05 21:24:36 +0100 |
| commit | a74af56dc1694fbeb8575825122d1081a30fe959 (patch) | |
| tree | 0a73cc5155c59a4ce407767920e423a67db7faca /src/southbridge/amd/sb800/chip.h | |
| parent | 252d39bb154d560257edcc61e4e2cd89f4614477 (diff) | |
| download | coreboot-a74af56dc1694fbeb8575825122d1081a30fe959.tar.xz | |
Overhaul speedstep code
This adds proper support for turbo and super-low-frequency modes.
Calculation of the p-states has been rewritten and moved into an
extra file speedstep.c so it can be used for non-acpi stuff like
EMTTM table generation.
It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300
(Yonah) processor.
Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1658
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/sb800/chip.h')
0 files changed, 0 insertions, 0 deletions