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| author | Zheng Bao <zheng.bao@amd.com> | 2011-01-20 05:59:22 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2011-01-20 05:59:22 +0000 |
| commit | a4da254a39cf8d2d98140c12b48b3163192594dd (patch) | |
| tree | c1cf7340a01f29e4ac1646ff3761da23a6d678c2 /src/southbridge/amd/sb800/sb800.h | |
| parent | 79c04d559a54e1480e59039468bee1956c039d61 (diff) | |
| download | coreboot-a4da254a39cf8d2d98140c12b48b3163192594dd.tar.xz | |
S3 feanture of SB800. Compiliant with SB700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/sb800/sb800.h')
| -rw-r--r-- | src/southbridge/amd/sb800/sb800.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h index 870e36ad97..cd9fb9ba9c 100644 --- a/src/southbridge/amd/sb800/sb800.h +++ b/src/southbridge/amd/sb800/sb800.h @@ -24,6 +24,8 @@ #include "chip.h" /* Power management index/data registers */ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 #define PM_INDEX 0xcd6 #define PM_DATA 0xcd7 #define PM2_INDEX 0xcd0 @@ -47,6 +49,8 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12 +void sb800_enable(device_t dev); + #ifdef __PRE_RAM__ void sb800_lpc_port80(void); void sb800_pci_port80(void); @@ -55,7 +59,9 @@ void sb800_clk_output_48Mhz(void); /* void sb800_setup_sata_phys(struct device *dev); */ #endif -void sb800_enable(device_t dev); +int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); + void sb800_enable_usbdebug(unsigned int port); #endif /* SB800_H */ |