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authorAntonello Dettori <dev@dettori.io>2016-09-03 10:45:33 +0200
committerMartin Roth <martinroth@google.com>2016-09-13 17:19:12 +0200
commit66a02c1ef3d181f9d83bb6847f14e812ae1a0a8d (patch)
tree169145b839a987f8b37112b89942219cf348e981 /src/southbridge/amd/sb800
parent6cf441523a216cecea1eb535382fc86e5ad923f9 (diff)
downloadcoreboot-66a02c1ef3d181f9d83bb6847f14e812ae1a0a8d.tar.xz
southbridge/amd/sb800: transition away from device_t
Replace the use of the old device_t definition inside southbridge/amd/sb800. Change-Id: I488cde4504128331106f50b34869905e30f5ab83 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16480 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/sb800')
-rw-r--r--src/southbridge/amd/sb800/early_setup.c14
-rw-r--r--src/southbridge/amd/sb800/sb800.h3
2 files changed, 10 insertions, 7 deletions
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index ac0691785b..070c1f535b 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -73,7 +73,7 @@ static void sb800_acpi_init(void)
/* RPR 2.28 Get SB ASIC Revision.*/
static u8 get_sb800_revision(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 rev_id;
u8 rev = 0;
@@ -123,7 +123,7 @@ void sb800_clk_output_48Mhz(void)
static void sb800_lpc_init(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
dev = PCI_DEV(0, 0x14, 0);
@@ -166,7 +166,7 @@ static void sb800_lpc_init(void)
/* what is its usage? */
static u32 get_sbdn(u32 bus)
{
- device_t dev;
+ pci_devfn_t dev;
/* Find the device. */
dev = PCI_DEV(bus, 0x14, 0);//pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
@@ -238,7 +238,7 @@ void soft_reset(void)
void sb800_pci_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* P2P Bridge */
dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
@@ -344,7 +344,7 @@ struct pm_entry const pm_table[] =
void sb800_lpc_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* Enable LPC controller */
byte = pmio_read(0xEC);
@@ -361,7 +361,7 @@ void sb800_lpc_port80(void)
/* sbDevicesPorInitTable */
static void sb800_devices_por_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 byte;
printk(BIOS_INFO, "sb800_devices_por_init()\n");
@@ -543,7 +543,7 @@ static void sb800_pmio_por_init(void)
*/
static void sb800_pci_cfg(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index 6a037cf4e8..b36d9bfad5 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -42,7 +42,10 @@ void pm_iowrite(u8 reg, u8 value);
u8 pm_ioread(u8 reg);
void pm2_iowrite(u8 reg, u8 value);
u8 pm2_ioread(u8 reg);
+
+#ifndef __SIMPLE_DEVICE__
void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
+#endif
#define REV_SB800_A11 0x11
#define REV_SB800_A12 0x12