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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-08-15 16:27:06 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-08-29 18:36:20 +0200 |
| commit | 8101aa6bb02c586cd0d1ab2cf99148329319aaf9 (patch) | |
| tree | 5609cabef4a330fa5438c74c749f763c39565693 /src/southbridge/amd/sb800 | |
| parent | 24100100181bd770ce0f1181a1770a0808790cde (diff) | |
| download | coreboot-8101aa6bb02c586cd0d1ab2cf99148329319aaf9.tar.xz | |
usbdebug: Support choice of EHCI controller
Nowadays, chipsets or boards do not only have one USB port with the
capabilities of a debug port but several ones. Some of these ports are
easier accessible than others, so making them configurable is also necessary.
This change adds infrastructure to switch between EHCI controllers,
but does not implement it for any chipset.
Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3438
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge/amd/sb800')
| -rw-r--r-- | src/southbridge/amd/sb800/enable_usbdebug.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 6422fa2295..92778698f2 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -30,12 +30,16 @@ #define SB800_DEVN_BASE 0 #endif -#define EHCI_EOR 0x20 #define DEBUGPORT_MISC_CONTROL 0x80 -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; + return PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2); +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +{ + u32 base_regs = pci_ehci_base_regs(dev); u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ @@ -47,14 +51,12 @@ void set_debug_port(unsigned int port) } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), - EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), - PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, EHCI_BAR_INDEX, base); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } |