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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-11 17:49:06 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-23 23:02:16 +0100 |
| commit | 44e4a4e4db23677c960591d3209004f4f8b80326 (patch) | |
| tree | 9632043a5f0c475ede792b585b71c60022913e4a /src/southbridge/amd/sr5650/cmn.h | |
| parent | ff8ccf05b04714ae86ed947841de718699a09d2c (diff) | |
| download | coreboot-44e4a4e4db23677c960591d3209004f4f8b80326.tar.xz | |
southbridge/amd/sr5650: Add IOMMU support
Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12044
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/cmn.h')
| -rw-r--r-- | src/southbridge/amd/sr5650/cmn.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index db27d4f455..0c0fd29ca7 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,8 @@ #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ #define NBMC_INDEX 0xE8 #define NBPCIE_INDEX 0xE0 +#define L2CFG_INDEX 0xF0 +#define L1CFG_INDEX 0xF8 #define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 |