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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-28 21:20:04 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:29:13 +0200 |
| commit | 1bcd7fcb6199528fc82685e161d6b39f273a1962 (patch) | |
| tree | 90e07ca28aa8514375b27b9c638a33701f921d52 /src/southbridge/amd/sr5650/early_setup.c | |
| parent | 15279a9696c70b82c2223264a505da9122f9aa7b (diff) | |
| download | coreboot-1bcd7fcb6199528fc82685e161d6b39f273a1962.tar.xz | |
src/southbridge: Capitalize CPU, RAM and ROM
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15941
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Diffstat (limited to 'src/southbridge/amd/sr5650/early_setup.c')
| -rw-r--r-- | src/southbridge/amd/sr5650/early_setup.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 1fc0427a36..a96b127cb2 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -343,7 +343,7 @@ static void sr5650_por_pcicfg_init(device_t nb_dev) set_nbcfg_enable_bits(nb_dev, 0x20, ~0, 0x0); set_nbcfg_enable_bits(nb_dev, 0x84, ~0, 0x03000010); - /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge + /* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation * BMMsgEn */ set_nbcfg_enable_bits(nb_dev, 0x4C, (u8)(~0x00), 0x52042); |