diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/southbridge/amd/sr5650/early_setup.c | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/early_setup.c')
| -rw-r--r-- | src/southbridge/amd/sr5650/early_setup.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 96adfb5bdd..543cb0efbf 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <option.h> #include <reset.h> #include "sr5650.h" @@ -309,9 +310,9 @@ void fam10_optimization(void) return; printk(BIOS_INFO, "fam10_optimization()\n"); - msr = rdmsr(0xC001001F); + msr = rdmsr(NB_CFG_MSR); msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */ - wrmsr(0xC001001F, msr); + wrmsr(NB_CFG_MSR, msr); cpu_f0 = PCI_DEV(0, 0x18, 0); cpu_f2 = PCI_DEV(0, 0x18, 2); |