diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-13 17:45:12 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-23 23:03:34 +0100 |
| commit | a8c6c7f30c2793aff4f1ab8d01954bbaced2b4ae (patch) | |
| tree | dd20b8c966d844d7dd86818069e2067557a022c5 /src/southbridge/amd/sr5650/pcie.c | |
| parent | 44e4a4e4db23677c960591d3209004f4f8b80326 (diff) | |
| download | coreboot-a8c6c7f30c2793aff4f1ab8d01954bbaced2b4ae.tar.xz | |
southbridge/amd/sr5650: Hide clock configuration device after setup is complete
Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12045
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/amd/sr5650/pcie.c')
| -rw-r--r-- | src/southbridge/amd/sr5650/pcie.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 4161c18ce9..762e632c2a 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -850,6 +850,9 @@ void sr56x0_lock_hwinitreg(void) /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); + + /* Hide clock configuration PCI device HIDE_CLKCFG_HEADER */ + set_nbmisc_enable_bits(nb_dev, 0x00, 0x00000100, 1 << 8); } /***************************************** |