diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/southbridge/amd/sr5650/pcie.c | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
| download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.xz | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/pcie.c')
| -rw-r--r-- | src/southbridge/amd/sr5650/pcie.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 9e2bd9233e..8986e676dc 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -454,14 +454,14 @@ static void EnableLclkGating(struct device *dev) reg = 0xE8; port = dev->path.pci.devfn >> 3; switch (port) { - //PCIE_CORE_INDEX_GPP1 + //PCIE_CORE_INDEX_GPP1 case 2: case 3: reg = 0x94; mask = 1 << 16; break; - //PCIE_CORE_INDEX_GPP2 + //PCIE_CORE_INDEX_GPP2 case 11: case 12: value = 1 << 28; @@ -479,7 +479,7 @@ static void EnableLclkGating(struct device *dev) value = 1 << 25; break; - //PCIE_CORE_INDEX_SB; + //PCIE_CORE_INDEX_SB; case 8: reg = 0x94; mask = 1 << 24; |