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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 21:20:04 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:29:13 +0200
commit1bcd7fcb6199528fc82685e161d6b39f273a1962 (patch)
tree90e07ca28aa8514375b27b9c638a33701f921d52 /src/southbridge/amd/sr5650/sr5650.c
parent15279a9696c70b82c2223264a505da9122f9aa7b (diff)
downloadcoreboot-1bcd7fcb6199528fc82685e161d6b39f273a1962.tar.xz
src/southbridge: Capitalize CPU, RAM and ROM
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Diffstat (limited to 'src/southbridge/amd/sr5650/sr5650.c')
-rw-r--r--src/southbridge/amd/sr5650/sr5650.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 818b0e646c..d28adfc042 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -564,7 +564,7 @@ void sr5650_nb_pci_table(device_t nb_dev)
printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16);
temp32 = pci_read_config32(nb_dev, 0x84);
printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32);
- //Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+ //Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge
//Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
pci_write_config8(nb_dev, 0x4c, 0x42);
temp8 = pci_read_config8(nb_dev, 0x4e);
@@ -605,7 +605,7 @@ void sr5650_nb_pci_table(device_t nb_dev)
* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
* 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1
-* case 0 will be called twice, one is by cpu in hypertransport.c line458,
+* case 0 will be called twice, one is by CPU in hypertransport.c line458,
* the other is by sr5650.
***********************************************/
void sr5650_enable(device_t dev)