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| author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 12:37:58 -0600 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 00:20:59 +0200 |
| commit | 00c8c4a31632150fa711493f39e727da950ebe9f (patch) | |
| tree | f3bad2e78ddb6999ad551a73f05c049a266a14ab /src/southbridge/amd/sr5650/sr5650.h | |
| parent | 09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff) | |
| download | coreboot-00c8c4a31632150fa711493f39e727da950ebe9f.tar.xz | |
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/sr5650.h')
| -rwxr-xr-x[-rw-r--r--] | src/southbridge/amd/sr5650/sr5650.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h index 5da354493b..1b5112b7c2 100644..100755 --- a/src/southbridge/amd/sr5650/sr5650.h +++ b/src/southbridge/amd/sr5650/sr5650.h @@ -103,6 +103,10 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); void enable_pcie_bar3(device_t nb_dev); void disable_pcie_bar3(device_t nb_dev); +void enable_sr5650_dev8(void); +void sr5650_htinit(void); +void sr5650_early_setup(void); +void sr5650_before_pci_init(void); void sr5650_enable(device_t dev); void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port); void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port); @@ -112,8 +116,9 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); void pcie_config_misc_clk(device_t nb_dev); void fam10_optimization(void); -void disable_pcie_bridge(void); +void sr5650_disable_pcie_bridge(void); u32 get_vid_did(device_t dev); void sr5650_nb_pci_table(device_t nb_dev); void init_gen2(device_t nb_dev, device_t dev, u8 port); +void sr56x0_lock_hwinitreg(void); #endif /* SR5650_H */ |