southbridge/amd amd81XX, cs553X & sr5650 spelling fixes

Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.

Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7842
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

4 files changed, 10 insertions, 10 deletions

diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index e8fb9561f7..64c69e5e00 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -229,11 +229,11 @@ void sr5650_htinit(void)
 		set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x1);
 		/* Enables error-retry mode */
 		set_nbcfg_enable_bits(sr5650_f0, 0x44, 0x1, 0x1);
-		/* Enables scrambling and Disalbes command throttling */
+		/* Enables scrambling and Disables command throttling */
 		set_nbcfg_enable_bits(sr5650_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14));
 		/* Enables transmitter de-emphasis */
 		set_nbcfg_enable_bits(sr5650_f0, 0xa4, 1 << 31, 1 << 31);
-		/* Enabels transmitter de-emphasis level */
+		/* Enables transmitter de-emphasis level */
 		/* Sets training 0 time */
 		set_nbcfg_enable_bits(sr5650_f0, 0xa0, 0x3F, 0x14);
 
@@ -258,7 +258,7 @@ void sr5650_htinit(void)
 		set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
 
 		/* Sets Training 0 Time. See T0Time table for encodings */
-		/* AGESA have set it to recommanded value already
+		/* AGESA have set it to recommended value already
 		 * The recommended values are 14h(2us) if F0x[18C:170][LS2En]=0
 		 * and 26h(12us) if F0x[18C:170][LS2En]=1
 		 */
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 809675c851..51873bfbf7 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -589,8 +589,8 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	   For Hot-Plug Slots: Advertise TX L0s and L1 exit latency.
 	   TX L0s exit latency to be 110b: 2us to 4us.
 	   L1 exit latency to be 111b: more than 64us.*/
-	//set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for htplg. */
-	set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for htplg. */
+	//set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for hotplug. */
+	set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for hotplug. */
 	/* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to
 	   workaround credit control issue on PM_NAK
 	   message of SB700 and SB800. */
@@ -690,7 +690,7 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	case 13:
 		/* 4.4.2.step13.5. Blocks DMA traffic during C3 state */
 		set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
-		/* Enabels TLP flushing */
+		/* Enables TLP flushing */
 		set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
 
 		/* check port enable */
@@ -724,7 +724,7 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	/* Set Slot present 0x5A*/
 	pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24);
 
-	//PCIE-GPP1 TXCLK Clock Gating In L1  Late Core sttting - Maybe move somewhere else? */
+	//PCIE-GPP1 TXCLK Clock Gating In L1  Late Core setting - Maybe move somewhere else? */
 	set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0);
 	/* Enable powering down PLLs in L1 or L23 Ready states.
 	 * Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */
@@ -800,7 +800,7 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
 	reg = nbmisc_read_index(nb_dev, 0x8);
 	reg |= (1 << 31) | (1 << 15) | (1 << 13);	//asserts
 	nbmisc_write_index(nb_dev, 0x8, reg);
-	reg &= ~((1 << 31) | (1 << 15) | (1 << 13));	//De-aserts
+	reg &= ~((1 << 31) | (1 << 15) | (1 << 13));	//De-asserts
 	nbmisc_write_index(nb_dev, 0x8, reg);
 
 	reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG at bit 0-4 */
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 2a2d558a70..84d6d9af0c 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -410,7 +410,7 @@ void sr5650_enable(device_t dev)
 				       (dev->enabled ? 0 : 1) << (7 + dev_ind));
 		if (dev->enabled)
 			sr5650_gpp_sb_init(nb_dev, dev, dev_ind);
-		/* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */
+		/* Don't call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */
 		break;
 	case 11:
 	case 12:	/* bus 0, dev 11,12, GPP2 */
diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h
index 85f85a1a5e..44243edb48 100644
--- a/src/southbridge/amd/sr5650/sr5650.h
+++ b/src/southbridge/amd/sr5650/sr5650.h
@@ -90,7 +90,7 @@ typedef struct __PCIE_CFG__ {
 * ------------------------------------------------- */
 extern PCIE_CFG AtiPcieCfg;
 
-/* ----------------- export funtions ----------------- */
+/* ----------------- export functions ----------------- */
 u32 nbpcie_p_read_index(device_t dev, u32 index);
 void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
 u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);