diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-04 07:22:02 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-03-06 11:38:10 +0000 |
| commit | c8b4d217d0679166486d1c830db244b05a8354fd (patch) | |
| tree | ece5c766a9444b1da7aef8d31fb928a77f58512e /src/southbridge/amd/sr5650 | |
| parent | 24b000a16004bc80a95ed3e0d7aafcbbf8c312ce (diff) | |
| download | coreboot-c8b4d217d0679166486d1c830db244b05a8354fd.tar.xz | |
sb/amd: Use simple PCI IO config access
Call the simple PCI config accessors directly.
Change-Id: I4aa0669179d6b01ab0713fd2a8b3cf4baf6e572f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/amd/sr5650')
| -rw-r--r-- | src/southbridge/amd/sr5650/pcie.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 763dd014af..f87fadbb08 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -893,7 +893,10 @@ void pcie_config_misc_clk(struct device *nb_dev) reg |= 1 << 0; pci_write_config32(nb_dev, 0x4c, reg); -#if 0 /* TODO: Check the mics clock later. */ +#if 0 + /* TODO: Check the mics clock later. */ + pci_devfn_t d0f1 = PCI_DEV(0, 0, 1); + if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) { /* TXCLK Clock Gating */ set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0); @@ -901,9 +904,9 @@ void pcie_config_misc_clk(struct device *nb_dev) set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(0, 1, 0x94); + reg = pci_io_read_config32(d0f1, 0x94); reg &= ~(1 << 16); - pci_cf8_conf1.write32(0, 1, 0x94, reg); + pci_io_write_config32(d0f1, 0x94, reg); } if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { @@ -913,9 +916,9 @@ void pcie_config_misc_clk(struct device *nb_dev) set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(0, 1, 0x94); + reg = pci_io_read_config32(d0f1, 0x94); reg &= ~(1 << 24); - pci_cf8_conf1.write32(0, 1, 0x94, reg); + pci_io_write_config32(d0f1, 0x94, reg); } #endif |