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| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-05-05 15:50:17 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-08 00:38:11 +0200 |
| commit | f8f00629e3b5e129a5962fed1b886034f45e844a (patch) | |
| tree | deda750cdf6f034467d33d73daa1481832df33d2 /src/southbridge/amd/sr5650 | |
| parent | c0e16e7024fbeb11975f0834a5d5d6c0d9f2e34e (diff) | |
| download | coreboot-f8f00629e3b5e129a5962fed1b886034f45e844a.tar.xz | |
Some more #if cleanup
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} +
(manual tweak since it hit a false positive)
Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} +
Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1006
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/sr5650')
| -rw-r--r-- | src/southbridge/amd/sr5650/early_setup.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 32bdd7f28a..0f54ba356c 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -51,7 +51,7 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) /* family 10 only, for reg > 0xFF */ -#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -220,7 +220,7 @@ void sr5650_htinit(void) /* Enable Protocol checker */ set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); -#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ /* HT3 mode, RPR 5.4.3 */ set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); @@ -270,7 +270,7 @@ void sr5650_htinit(void) } } -#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; |