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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/southbridge/amd/sr5650 | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
| download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.xz | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/sr5650')
| -rw-r--r-- | src/southbridge/amd/sr5650/cmn.h | 12 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/pcie.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/sr5650.c | 4 |
3 files changed, 11 insertions, 11 deletions
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index e44d1e89c0..859e15dd62 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -19,12 +19,12 @@ #include <arch/io.h> -#define NBMISC_INDEX 0x60 -#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ -#define NBMC_INDEX 0xE8 -#define NBPCIE_INDEX 0xE0 -#define L2CFG_INDEX 0xF0 -#define L1CFG_INDEX 0xF8 +#define NBMISC_INDEX 0x60 +#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ +#define NBMC_INDEX 0xE8 +#define NBPCIE_INDEX 0xE0 +#define L2CFG_INDEX 0xF0 +#define L1CFG_INDEX 0xF8 #define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 9e2bd9233e..8986e676dc 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -454,14 +454,14 @@ static void EnableLclkGating(struct device *dev) reg = 0xE8; port = dev->path.pci.devfn >> 3; switch (port) { - //PCIE_CORE_INDEX_GPP1 + //PCIE_CORE_INDEX_GPP1 case 2: case 3: reg = 0x94; mask = 1 << 16; break; - //PCIE_CORE_INDEX_GPP2 + //PCIE_CORE_INDEX_GPP2 case 11: case 12: value = 1 << 28; @@ -479,7 +479,7 @@ static void EnableLclkGating(struct device *dev) value = 1 << 25; break; - //PCIE_CORE_INDEX_SB; + //PCIE_CORE_INDEX_SB; case 8: reg = 0x94; mask = 1 << 24; diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 1962ea3277..fae26899ec 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -427,7 +427,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) { dword |= (0x1 << 0); l2cfg_ind_write_index(nb_dev, 0x44, dword); -// if (get_nb_rev(nb_dev) == REV_SR5650_A21) { +// if (get_nb_rev(nb_dev) == REV_SR5650_A21) { dword = l2cfg_ind_read_index(nb_dev, 0x7); dword |= (0x1 << 1); l2cfg_ind_write_index(nb_dev, 0x7, dword); @@ -479,7 +479,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) { dword = l2cfg_ind_read_index(nb_dev, 0x6); dword |= (0x1 << 8); l2cfg_ind_write_index(nb_dev, 0x6, dword); -// } +// } l2cfg_ind_write_index(nb_dev, 0x52, 0xf0000002); |