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| author | Martin Roth <martinroth@google.com> | 2017-06-24 21:30:14 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-30 03:44:59 +0000 |
| commit | 083504b66b5f3b281221f0a8f4fd62a4d9071287 (patch) | |
| tree | dcf6fcb31f5d7ee760634c86b0fc06a7383e6d94 /src/southbridge/amd/sr5650 | |
| parent | 5f9c6734fc9bbe69c007c46c8ec6f314bd5522a8 (diff) | |
| download | coreboot-083504b66b5f3b281221f0a8f4fd62a4d9071287.tar.xz | |
southbridge/amd: add IS_ENABLED() around Kconfig symbol references
Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sr5650')
| -rw-r--r-- | src/southbridge/amd/sr5650/early_setup.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index fce25ab41a..6b4d81a62a 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -50,7 +50,8 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) /* family 10 only, for reg > 0xFF */ -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -221,7 +222,8 @@ void sr5650_htinit(void) /* Enable Protocol checker */ set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) /* HT3 mode, RPR 5.4.3 */ set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); @@ -299,7 +301,8 @@ void sr5650_htinit_dect_and_enable_isochronous_link(void) } } -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; |