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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-03 06:10:23 +0300
committerPatrick Georgi <pgeorgi@google.com>2018-06-04 08:46:06 +0000
commit1bad4ce421188748d1c3dd6bafe3863cbb21dd24 (patch)
tree6e023a6ef1f1f731a61d9fa86ef9c2747f441927 /src/southbridge/amd/sr5650
parent2d7825b0fce070f41ef35b7fdcf599550663dbe9 (diff)
downloadcoreboot-1bad4ce421188748d1c3dd6bafe3863cbb21dd24.tar.xz
sb/amd/sr5650: Fix invalid function declarations
Change-Id: I5034debc2296352e698898c20910a2d76071e30a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/sr5650')
-rw-r--r--src/southbridge/amd/sr5650/cmn.h4
-rw-r--r--src/southbridge/amd/sr5650/sr5650.c3
2 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
index 0c0fd29ca7..e44d1e89c0 100644
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -146,4 +146,8 @@ static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32
nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
}
}
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
#endif /* __SR5650_CMN_H__ */
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index ec78467d0e..1962ea3277 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -32,9 +32,6 @@
/*
* extern function declaration
*/
-extern void set_pcie_dereset(void);
-extern void set_pcie_reset(void);
-
struct resource * sr5650_retrieve_cpu_mmio_resource() {
struct device *domain;
struct resource *res;