summaryrefslogtreecommitdiff
path: root/src/southbridge/amd/sr5650
diff options
context:
space:
mode:
authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2017-09-29 02:45:31 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-10-31 09:57:06 +0000
commitec48c749c254f5ea353b5deea4b207df3cf7a6a6 (patch)
treef8e330b9c38d0454d85d82aca7fa2a7475f3865b /src/southbridge/amd/sr5650
parent6e70d67824e7c12a590038379866dbc7d7418fea (diff)
downloadcoreboot-ec48c749c254f5ea353b5deea4b207df3cf7a6a6.tar.xz
AMD boards: Fix function name (soft_reset) in message
Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sr5650')
-rw-r--r--src/southbridge/amd/sr5650/early_setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 88ed41cb41..98b60fd152 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -293,7 +293,7 @@ void sr5650_htinit_dect_and_enable_isochronous_link(void)
if (!((pci_read_config32(sr5650_f0, 0xc8) >> 12) & 0x1)) {
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
- die("After soft_reset_x - shouldn't see this message!!!\n");
+ die("After soft_reset - shouldn't see this message!!!\n");
}
}
}