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authorPaul Menzel <paulepanter@users.sourceforge.net>2015-10-25 22:27:42 +0100
committerMartin Roth <martinroth@google.com>2015-10-29 17:06:36 +0100
commit114a9489ed688403e202ada5eb22fc171a769594 (patch)
treef63218707fa784708425ef5b0308e479666b2131 /src/southbridge/amd
parenteabce729a71dc161128882cba23af8bd00bff06d (diff)
downloadcoreboot-114a9489ed688403e202ada5eb22fc171a769594.tar.xz
amd/cimx/sb800/late.c: Add comment in `sb800_init()`
Add a comment explaining what `abcfg_reg(0xc0, 0x01FF, 0x0F4)` does. This is a follow-up for commit 24501cae (AMD cimx/sb800: Initially enable all GPP ports). Change-Id: I5ac263ee088d36a7f7a2d03c1454ed647faa7147 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index cf7fb1cc0c..8ed0f82cad 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -268,6 +268,7 @@ static void sb800_init(void *chip_info)
sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
sb800_cimx_config(sb_config);
+ /* Initially enable all GPP ports 0 to 3 */
abcfg_reg(0xc0, 0x01FF, 0x0F4);
}