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authorTimothy Pearson <tpearson@raptorengineering.com>2017-04-13 17:02:58 -0500
committerMartin Roth <martinroth@google.com>2017-04-15 23:07:49 +0200
commit66d5b924405010b48121dba54b781886546538d7 (patch)
treef4f462bc9b5871bc7769d7c27d77e9be0e442321 /src/southbridge/amd
parent4bc9c28811706287753c084c696b59a116269f05 (diff)
downloadcoreboot-66d5b924405010b48121dba54b781886546538d7.tar.xz
sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used
Do not map LPC ROM into the system memory space when SPI Flash is configured instead of an LPC ROM. This resolves a long-standing hard boot hang issue on the ASUS KGPE-D16 and related systems; in a nutshell, the incorrectly mapped LPC ROM overrode low memory required by ramstage, causing decompressed ramstage layout-dependent vectoring to romstage code and subsequent execution of random sections of romstage. Sometimes these random sections of romstage reconfigured the hardware in such a way that it could not access SPI Flash on the next boot attempt. Change-Id: I115e5d834f0ca99c2d9dbb5b9b5badbea1d98574 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19280 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daniel Kulesz <daniel.ina1@googlemail.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/sb700/bootblock.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index dfa4102953..e77db5ced9 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -44,15 +44,13 @@ static void sb700_enable_rom(void)
dev = PCI_DEV(0, 0x14, 3);
- /* The LPC settings below work for SPI flash as well;
- * the hardware does not distinguish between LPC and SPI flash ROM
- * aside from offering additional side-channel access to SPI flash
- * via a separate register-based interface.
- */
-
- /* Decode variable LPC ROM address ranges 1 and 2. */
reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
- reg8 |= (1 << 3) | (1 << 4);
+ if (IS_ENABLED(CONFIG_SPI_FLASH))
+ /* Disable decode of variable LPC ROM address ranges 1 and 2. */
+ reg8 &= ~((1 << 3) | (1 << 4));
+ else
+ /* Decode variable LPC ROM address ranges 1 and 2. */
+ reg8 |= (1 << 3) | (1 << 4);
pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
/* LPC ROM address range 1: */