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authorStefan Reinauer <stepan@coresystems.de>2010-04-09 11:34:59 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-09 11:34:59 +0000
commit6a445e812604edaa0f11c99d835eddaeefa83d3b (patch)
treef8c0a89af9c72b4d8a040eced78c86d7b899abfc /src/southbridge/amd
parent7488e049df9899dd7062b2ffe393b3e9a6f50dc5 (diff)
downloadcoreboot-6a445e812604edaa0f11c99d835eddaeefa83d3b.tar.xz
zero warning days.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/rs690/rs690_gfx.c4
-rw-r--r--src/southbridge/amd/sb600/sb600_reset.c35
-rw-r--r--src/southbridge/amd/sb700/sb700_early_setup.c5
3 files changed, 8 insertions, 36 deletions
diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c
index 7f76a057ac..887c38e8de 100644
--- a/src/southbridge/amd/rs690/rs690_gfx.c
+++ b/src/southbridge/amd/rs690/rs690_gfx.c
@@ -34,6 +34,7 @@
#define CLK_CNTL_INDEX 0x8
#define CLK_CNTL_DATA 0xC
+#if 0
static u32 clkind_read(device_t dev, u32 index)
{
u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
@@ -41,6 +42,7 @@ static u32 clkind_read(device_t dev, u32 index)
*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
}
+#endif
static void clkind_write(device_t dev, u32 index, u32 data)
{
@@ -73,8 +75,6 @@ static void rs690_gfx_read_resources(device_t dev)
static void internal_gfx_pci_dev_init(struct device *dev)
{
u16 deviceid, vendorid;
- struct southbridge_amd_rs690_config *cfg =
- (struct southbridge_amd_rs690_config *)dev->chip_info;
deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
diff --git a/src/southbridge/amd/sb600/sb600_reset.c b/src/southbridge/amd/sb600/sb600_reset.c
index d6ea995a5c..af80576204 100644
--- a/src/southbridge/amd/sb600/sb600_reset.c
+++ b/src/southbridge/amd/sb600/sb600_reset.c
@@ -18,39 +18,10 @@
*/
#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <reset.h>
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
-
-typedef u32 device_t;
-
-static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outb(value, 0xCFC + (addr & 3));
-}
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(device_t dev, unsigned where)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
-}
-
-#include "../../../northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/reset_test.c"
void hard_reset(void)
{
diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c
index 5d2fde2a4c..8aca04d9a0 100644
--- a/src/southbridge/amd/sb700/sb700_early_setup.c
+++ b/src/southbridge/amd/sb700/sb700_early_setup.c
@@ -20,6 +20,7 @@
#ifndef _SB700_EARLY_SETUP_C_
#define _SB700_EARLY_SETUP_C_
+#include <reset.h>
#include <arch/cpu.h>
#include "sb700.h"
#include "sb700_smbus.c"
@@ -214,7 +215,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
pmio_write(0x89, 0x10);
}
-static void hard_reset(void)
+void hard_reset(void)
{
set_bios_reset();
@@ -223,7 +224,7 @@ static void hard_reset(void)
outb(0x0e, 0x0cf9);
}
-static void soft_reset(void)
+void soft_reset(void)
{
set_bios_reset();
/* link reset */