soutbridge/*/bootblock: Use pci_dev_t over device_t typedef

Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7193
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

8 files changed, 10 insertions, 10 deletions

diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index 65810facf3..3cdba8b907 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -33,7 +33,7 @@
 static void hudson_enable_rom(void)
 {
 	u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x14, 3);
 
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index ba3dc431a0..4c009890d0 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -26,7 +26,7 @@
 static void amd8111_enable_rom(void)
 {
 	u8 byte;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
 					  PCI_DEVICE_ID_AMD_8111_ISA), 0);
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 1027659d5c..4ddfb92ccf 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -24,7 +24,7 @@ static void sb700_enable_rom(void)
 {
 	u32 word;
 	u32 dword;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x14, 0x03);
 	/* SB700 LPC Bridge 0:20:3:44h.
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 4fd2739442..188ba291f9 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -23,7 +23,7 @@ static void enable_rom(void)
 {
 	u16 word;
 	u32 dword;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x14, 0x03);
 	/* SB800 LPC Bridge 0:20:3:44h.
@@ -57,7 +57,7 @@ static void enable_rom(void)
 static void enable_prefetch(void)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, 0x14, 0x03);
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
 
 	/* Enable PrefetchEnSPIFromHost */
 	dword = pci_io_read_config32(dev, 0xb8);
@@ -67,7 +67,7 @@ static void enable_prefetch(void)
 static void enable_spi_fast_mode(void)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, 0x14, 0x03);
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
 
 	// set temp MMIO base
 	volatile u32 *spi_base = (void *)0xa0000000;
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index 9108a8bb75..561904e942 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -23,7 +23,7 @@ static void sb900_enable_rom(void)
 {
   u32 word;
   u32 dword;
-  device_t dev;
+  pci_devfn_t dev;
 
   dev = PCI_DEV(0, 0x14, 0x03);
   /* SB900 LPC Bridge 0:20:3:44h.
diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index e31a96c8e3..94f5e6ee08 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -34,7 +34,7 @@
 static void sb600_enable_rom(void)
 {
 	u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
 			PCI_DEVICE_ID_ATI_SB600_LPC), 0);
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index c290806911..67da3fabec 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -35,7 +35,7 @@
 static void sb700_enable_rom(void)
 {
 	u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x14, 3);
 
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 9311b978f9..61ff284dd8 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -33,7 +33,7 @@
 static void sb800_enable_rom(void)
 {
 	u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x14, 3);