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authorJosef Kellermann <seppk@arcor.de>2011-02-14 19:19:58 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2011-02-14 19:19:58 +0000
commitcf37a5942fc4aecb8ceb71baf983eb29cc131da9 (patch)
tree2b4ff90a8039ceb5af0fe315b3417b0c52f95841 /src/southbridge/amd
parent144fe883388c54589cf6cfe6a7a879b4e7e6dd50 (diff)
downloadcoreboot-cf37a5942fc4aecb8ceb71baf983eb29cc131da9.tar.xz
Removed LPC DMA Deadlock workaround...
Setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in amdk8/coherent.c Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/rs690/gfx.c9
1 files changed, 1 insertions, 8 deletions
diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c
index 175ea71991..0308ce4497 100644
--- a/src/southbridge/amd/rs690/gfx.c
+++ b/src/southbridge/amd/rs690/gfx.c
@@ -114,7 +114,7 @@ static void rs690_internal_gfx_enable(device_t dev)
{
u32 l_dword;
int i;
- device_t k8_f0 = 0, k8_f2 = 0;
+ device_t k8_f2 = 0;
device_t nb_dev = dev_find_slot(0, 0);
printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
@@ -129,13 +129,6 @@ static void rs690_internal_gfx_enable(device_t dev)
/* set TOM */
rs690_set_tom(nb_dev);
- /* LPC DMA Deadlock workaround? */
- k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
- l_dword = pci_read_config32(k8_f0, 0x68);
- l_dword &= ~(1 << 22);
- l_dword |= (1 << 21);
- pci_write_config32(k8_f0, 0x68, l_dword);
-
/* Enable 64bit mode. */
set_nbmc_enable_bits(nb_dev, 0x5f, 0, 1 << 9);
set_nbmc_enable_bits(nb_dev, 0xb0, 0, 1 << 8);