diff options
author | Marc Jones <marcj303@gmail.com> | 2017-03-22 18:47:49 +0800 |
---|---|---|
committer | Marc Jones <marc@marcjonesconsulting.com> | 2017-04-26 02:21:53 +0200 |
commit | f962aa52d626f997f7749b4566e5fefca97ebcf2 (patch) | |
tree | 1ecc34671eb65beee9c7890b661139964c46087a /src/southbridge/amd | |
parent | a915cea289210b17b7df0845f8738363be659bb4 (diff) | |
download | coreboot-f962aa52d626f997f7749b4566e5fefca97ebcf2.tar.xz |
amd/pi/hudson: Add LPC IO decode enable function
Add a function to enable LPC IO decode AKA WideIO.
This can enable up to 3 regions, which may be 512 or 16
bytes wide.
Change-Id: I2bed3a99180188101e00b4431d634227e488cbda
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19160
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r-- | src/southbridge/amd/pi/hudson/early_setup.c | 88 | ||||
-rw-r--r-- | src/southbridge/amd/pi/hudson/hudson.h | 17 |
2 files changed, 105 insertions, 0 deletions
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 3de3c564d1..5f3f0ee858 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -16,6 +16,7 @@ #ifndef _HUDSON_EARLY_SETUP_C_ #define _HUDSON_EARLY_SETUP_C_ +#include <assert.h> #include <stdint.h> #include <arch/io.h> #include <arch/acpi.h> @@ -140,6 +141,93 @@ void hudson_lpc_decode(void) pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); } +static void enable_wideio(uint8_t port, uint16_t size) +{ + uint32_t wideio_enable[] = { + LPC_WIDEIO0_ENABLE, + LPC_WIDEIO1_ENABLE, + LPC_WIDEIO2_ENABLE + }; + uint32_t alt_wideio_enable[] = { + LPC_ALT_WIDEIO0_ENABLE, + LPC_ALT_WIDEIO1_ENABLE, + LPC_ALT_WIDEIO2_ENABLE + }; + pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + uint32_t tmp; + + /* Only allow port 0-2 */ + assert(port <= ARRAY_SIZE(wideio_enable)); + + if (size == 16) { + tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); + tmp |= alt_wideio_enable[port]; + pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); + } else { /* 512 */ + tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); + tmp &= ~alt_wideio_enable[port]; + pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); + } + + /* Enable the range */ + tmp = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + tmp |= wideio_enable[port]; + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, tmp); +} + +/* + * lpc_wideio_window() may be called any point in romstage, but take + * care that AGESA doesn't overwrite the range this function used. + * The function checks if there is an empty range and if all ranges are + * used the function throws an assert. The function doesn't check for a + * duplicate range, for ranges that can be merged into a single + * range, or ranges that overlap. + * + * The developer is expected to ensure that there are no conflicts. + */ +static void lpc_wideio_window(uint16_t base, uint16_t size) +{ + pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + u32 tmp; + + /* Support 512 or 16 bytes per range */ + assert(size == 512 || size == 16); + + /* Find and open Base Register and program it */ + tmp = pci_read_config32(dev, LPC_WIDEIO_GENERIC_PORT); + + if ((tmp & 0xFFFF) == 0) { /* WIDEIO0 */ + tmp |= base; + pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); + enable_wideio(0, size); + } else if ((tmp & 0xFFFF0000) == 0) { /* WIDEIO1 */ + tmp |= (base << 16); + pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); + enable_wideio(1, size); + } else { /* Check WIDEIO2 register */ + tmp = pci_read_config32(dev, LPC_WIDEIO2_GENERIC_PORT); + if ((tmp & 0xFFFF) == 0) { /* WIDEIO2 */ + tmp |= base; + pci_write_config32(dev, LPC_WIDEIO2_GENERIC_PORT, tmp); + enable_wideio(2, size); + } else { /* All WIDEIO locations used*/ + assert(0); + } + } +} + +void lpc_wideio_512_window(uint16_t base) +{ + assert(IS_ALIGNED(base, 512)); + lpc_wideio_window(base, 512); +} + +void lpc_wideio_16_window(uint16_t base) +{ + assert(IS_ALIGNED(base, 16)); + lpc_wideio_window(base, 16); +} + int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { int i; diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 6c08f2f1b4..9cc007090d 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -103,6 +103,20 @@ #define DECODE_ENABLE_ACPIUC_PORT BIT(30) #define DECODE_ENABLE_ADLIB_PORT BIT(31) +#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 +#define LPC_WIDEIO2_ENABLE BIT(25) +#define LPC_WIDEIO1_ENABLE BIT(24) +#define LPC_WIDEIO0_ENABLE BIT(2) + +#define LPC_WIDEIO_GENERIC_PORT 0x64 + +#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 +#define LPC_ALT_WIDEIO2_ENABLE BIT(3) +#define LPC_ALT_WIDEIO1_ENABLE BIT(2) +#define LPC_ALT_WIDEIO0_ENABLE BIT(0) + +#define LPC_WIDEIO2_GENERIC_PORT 0x90 + #define SPI_CNTRL0 0x00 #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) /* Nominal is 16.7MHz on older devices, 33MHz on newer */ @@ -169,6 +183,9 @@ void hudson_read_mode(u32 mode); void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void hudson_disable_4dw_burst(void); void hudson_set_readspeed(u16 norm, u16 fast); +void lpc_wideio_512_window(uint16_t base); +void lpc_wideio_16_window(uint16_t base); + int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); |