AGESA: Fix UMA calculations

Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.

Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.

Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

8 files changed, 96 insertions, 39 deletions

diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c
index 567cd12979..798a3bbf42 100644
--- a/src/southbridge/amd/agesa/hudson/ramtop.c
+++ b/src/southbridge/amd/agesa/hudson/ramtop.c
@@ -26,27 +26,21 @@ int acpi_get_sleep_type(void)
 	return (int)tmp;
 }
 
-#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
-
-#ifndef __PRE_RAM__
 void backup_top_of_ram(uint64_t ramtop)
 {
-	u32 dword = (u32) ramtop;
+	u32 dword = ramtop;
 	int nvram_pos = 0xf8, i; /* temp */
 	for (i = 0; i < 4; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
-		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
 		nvram_pos++;
 	}
 }
-#endif
 
 unsigned long get_top_of_ram(void)
 {
 	uint32_t xdata = 0;
 	int xnvram_pos = 0xf8, xi;
-	if (acpi_get_sleep_type() != 3)
-		return 0;
 	for (xi = 0; xi < 4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
@@ -55,5 +49,3 @@ unsigned long get_top_of_ram(void)
 	}
 	return (unsigned long) xdata;
 }
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc
index ab668e2024..0b9ee9ce33 100644
--- a/src/southbridge/amd/cimx/sb700/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb700/Makefile.inc
@@ -19,9 +19,11 @@
 romstage-y += early.c
 romstage-y += smbus.c smbus_spd.c
 romstage-y += reset.c
+romstage-y += ramtop.c
 
 ramstage-y += late.c
 ramstage-y += reset.c
+ramstage-y += ramtop.c
 
 ramstage-y   += smbus.c
 ramstage-y   += lpc.c
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
index 1639f087a1..5a8faa85b6 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -20,23 +20,6 @@
 #include <console/console.h>	/* printk */
 #include <cbmem.h>
 
-#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
-
-#define BIOSRAM_INDEX   0xcd4
-#define BIOSRAM_DATA    0xcd5
-
-void backup_top_of_ram(uint64_t ramtop)
-{
-	u32 dword = (u32) ramtop;
-	int nvram_pos = 0xfc, i;
-	for (i = 0; i < 4; i++) {
-		outb(nvram_pos, BIOSRAM_INDEX);
-		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
-		nvram_pos++;
-	}
-}
-#endif
-
 void lpc_read_resources(device_t dev)
 {
 	struct resource *res;
diff --git a/src/southbridge/amd/cimx/sb700/ramtop.c b/src/southbridge/amd/cimx/sb700/ramtop.c
new file mode 100644
index 0000000000..f59a9a346b
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/ramtop.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <cbmem.h>
+#include <southbridge/amd/cimx/cimx_util.h>
+
+void backup_top_of_ram(uint64_t ramtop)
+{
+	u32 dword = ramtop;
+	int nvram_pos = 0xfc, i;
+	for (i = 0; i < 4; i++) {
+		outb(nvram_pos, BIOSRAM_INDEX);
+		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
+		nvram_pos++;
+	}
+}
+
+unsigned long get_top_of_ram(void)
+{
+	u32 xdata = 0;
+	int xnvram_pos = 0xfc, xi;
+	for (xi = 0; xi < 4; xi++) {
+		outb(xnvram_pos, BIOSRAM_INDEX);
+		xdata &= ~(0xff << (xi * 8));
+		xdata |= inb(BIOSRAM_DATA) << (xi *8);
+		xnvram_pos++;
+	}
+	return (unsigned long) xdata;
+}
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 7c31278f2a..0511fb3074 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -30,8 +30,8 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 
-romstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c
-ramstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c
+romstage-y += ramtop.c
+ramstage-y += ramtop.c
 
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c
diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
index 44a49600ac..4d5b9a8a62 100644
--- a/src/southbridge/amd/cimx/sb800/ramtop.c
+++ b/src/southbridge/amd/cimx/sb800/ramtop.c
@@ -26,27 +26,21 @@ int acpi_get_sleep_type(void)
 	return (int)tmp;
 }
 
-#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
-
-#ifndef __PRE_RAM__
 void backup_top_of_ram(uint64_t ramtop)
 {
-	u32 dword = (u32) ramtop;
+	u32 dword = ramtop;
 	int nvram_pos = 0xf8, i; /* temp */
 	for (i = 0; i < 4; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
-		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
 		nvram_pos++;
 	}
 }
-#endif
 
 unsigned long get_top_of_ram(void)
 {
 	u32 xdata = 0;
 	int xnvram_pos = 0xf8, xi;
-	if (acpi_get_sleep_type() != 3)
-		return 0;
 	for (xi = 0; xi < 4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
@@ -55,5 +49,3 @@ unsigned long get_top_of_ram(void)
 	}
 	return (unsigned long) xdata;
 }
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc
index 05ebaead18..b09180cfa7 100644
--- a/src/southbridge/amd/cimx/sb900/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb900/Makefile.inc
@@ -20,11 +20,13 @@ romstage-y += cfg.c
 romstage-y += early.c
 romstage-y += smbus.c smbus_spd.c
 romstage-y += reset.c
+romstage-y += ramtop.c
 
 ramstage-y += cfg.c
 ramstage-y += early.c
 ramstage-y += late.c
 ramstage-y += reset.c
+ramstage-y += ramtop.c
 
 ramstage-y   += smbus.c
 ramstage-y   += lpc.c
diff --git a/src/southbridge/amd/cimx/sb900/ramtop.c b/src/southbridge/amd/cimx/sb900/ramtop.c
new file mode 100644
index 0000000000..34e8364379
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/ramtop.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <cbmem.h>
+#include <southbridge/amd/cimx/cimx_util.h>
+
+void backup_top_of_ram(uint64_t ramtop)
+{
+	u32 dword = ramtop;
+	int nvram_pos = 0xf8, i; /* temp */
+	for (i = 0; i < 4; i++) {
+		outb(nvram_pos, BIOSRAM_INDEX);
+		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
+		nvram_pos++;
+	}
+}
+
+unsigned long get_top_of_ram(void)
+{
+	u32 xdata = 0;
+	int xnvram_pos = 0xf8, xi;
+	for (xi = 0; xi < 4; xi++) {
+		outb(xnvram_pos, BIOSRAM_INDEX);
+		xdata &= ~(0xff << (xi * 8));
+		xdata |= inb(BIOSRAM_DATA) << (xi *8);
+		xnvram_pos++;
+	}
+	return (unsigned long) xdata;
+}